MAX1748 데이터 시트보기 (PDF) - Maxim Integrated
부품명
상세내역
제조사
MAX1748 Datasheet PDF : 16 Pages
| |||
Triple-Output TFT-LCD
DC-DC Converters
Pin Description (continued)
PIN
NAME
FUNCTION
8
FBN
Negative Charge-Pump Regulator Feedback Input. Regulates to 0V nominal.
9
SHDN
Active-Low Logic-Level Shutdown Input. Connect SHDN to IN for normal operation.
10
DRVN Negative Charge-Pump Driver Output. Output high level is VSUPN, and low level is PGND.
11
SUPN Negative Charge-Pump Driver Supply Voltage. Bypass to PGND with a 0.1µF capacitor.
12
DRVP
Positive Charge-Pump Driver Output. Output high level is VSUPP, and low level is PGND.
13
SUPP Positive Charge-Pump Driver Supply Voltage. Bypass to PGND with a 0.1µF capacitor.
14
PGND Power Ground. Connect to GND underneath the IC.
15
LX
Main Boost Regulator Power MOSFET n-Channel Drain. Connect output diode and output capacitor
as close to PGND as possible.
16
TGND Must be connected to ground.
Detailed Description
The MAX1748/MAX8726 are highly efficient triple-output
power supplies for TFT-LCD applications. These devices
contain one high-power step-up converter and two low-
power charge pumps. The primary boost converter uses
an internal n-channel MOSFET to provide maximum
efficiency and to minimize the number of external compo-
nents. The output voltage of the main boost converter
(VMAIN) can be set from VIN to 13V with external resistors.
The dual charge pumps independently regulate a posi-
tive output (VPOS) and a negative output (VNEG). These
low-power outputs use external diode and capacitor
stages (as many stages as required) to regulate output
voltages up to +40V and down to -40V. A proprietary
regulation algorithm minimizes output ripple as well as
capacitor sizes for both charge pumps.
Also included in the MAX1748/MAX8726 is a precision
1.25V reference that sources up to 50µA, logic shut-
down, soft-start, power-up sequencing, fault detection,
and an active-low open-drain ready output.
Main Boost Converter
The MAX1748/MAX8726 main step-up converter
switches at a constant 1MHz internal oscillator frequen-
cy to allow the use of small inductors and output
capacitors. The MOSFET switch pulse width is modulat-
ed to control the power transferred on each switching
cycle and to regulate the output voltage.
During PWM operation, the internal clock’s rising edge
sets a flip-flop, which turns on the n-channel MOSFET
(Figure 1). The switch turns off when the sum of the
voltage-error, slope-compensation, and current-feed-
back signals trips the multi-input comparator and
resets the flip-flop. The switch remains off for the rest of
the clock cycle. Changes in the output-voltage error
signal shift the switch current trip level, consequently
modulating the MOSFET duty cycle.
Dual Charge-Pump Regulator
The MAX1748/MAX8726 contain two individual low-
power charge pumps. One charge pump inverts the
supply voltage (SUPN) and provides a regulated nega-
tive output voltage. The second charge pump doubles
the supply voltage (SUPP) and provides a regulated
positive output voltage. The MAX1748/MAX8726 con-
tain internal p-channel and n-channel MOSFETs to con-
trol the power transfer. The internal MOSFETs switch at
a constant 500kHz (0.5 x fOSC).
Negative Charge Pump
During the first half-cycle, the p-channel MOSFET turns
on and the flying capacitor C5 charges to VSUPN minus a
diode drop (Figure 2). During the second half-cycle, the
p-channel MOSFET turns off, and the n-channel MOSFET
turns on, level shifting C5. This connects C5 in parallel
with the reservoir capacitor C6. If the voltage across C6
minus a diode drop is lower than the voltage across C5,
charge flows from C5 to C6 until the diode (D5) turns off.
The amount of charge transferred to the output is
controlled by the variable n-channel on-resistance.
Positive Charge Pump
During the first half-cycle, the n-channel MOSFET turns
on and charges the flying capacitor C3 (Figure 3). This
initial charge is controlled by the variable n-channel on-
resistance. During the second half-cycle, the n-channel
MOSFET turns off and the p-channel MOSFET turns on,
level shifting C3 by VSUPP volts. This connects C3 in par-
allel with the reservoir capacitor C4. If the voltage across
C4 plus a diode drop (VPOS + VDIODE) is smaller than the
level-shifted flying capacitor voltage (VC3 + VSUPP),
charge flows from C3 to C4 until the diode (D3) turns off.
8 _______________________________________________________________________________________
Share Link: 