DatasheetQ Logo
Electronic component search and free download site. Transistors,MosFET ,Diode,Integrated circuits

MAX1809 데이터 시트보기 (PDF) - Maxim Integrated

부품명
상세내역
제조사
MAX1809 Datasheet PDF : 17 Pages
1 2 3 4 5 6 7 8 9 10 Next Last
3A, 1MHz, DDR Memory Termination Supply
to maximum DC load current. A higher value of LIR
allows smaller inductance but results in higher losses
and ripple. A good compromise between size and losses
is found at approximately a 25% ripple current to load
current ratio (LIR = 0.25).
( ) L =
VOUT × tOFF
( ) ISOURCE ISINK × LIR
The peak inductor current at full load is calculated by:
( ) IPEAK = IOUT +
VOUT × tOFF
2×L
where IOUT is the maximum source or sink current.
Choose an inductor with a saturation current at least as
high as the peak inductor current. Additionally, verify
the peak inductor current while sourcing output current
(IOUT = ISOURCE) does not exceed the positive current
limit. The inductor selected should exhibit low losses at
the chosen operating frequency.
Input Capacitor Selection
The input filter capacitor reduces peak currents and
noise at the voltage source. Use a low-ESR and low-
ESL capacitor located no further than 5mm from IN.
Select the input capacitor according to the RMS input
ripple-current requirements and voltage rating:
( )
IRIPPLE
=
IOUT

VOUT ×
VIN VOUT
VIN

where IRIPPLE = input RMS current ripple.
Output Capacitor Selection
The output filter capacitor affects the output voltage
ripple, output load-transient response, and feedback
loop stability. The output filter capacitor must have low
enough ESR to meet output ripple and load transient
requirements, yet have high enough ESR to satisfy sta-
bility requirements. Also, the capacitance value must
be high enough to guarantee stability and absorb the
inductor energy going from a full-load sourcing to full-
load sinking condition without exceeding the maximum
output tolerance.
For stable operation, the MAX1809 requires a minimum
feedback ripple voltage of VRIPPLE 1% VEXTREF.
The minimum ESR of the output capacitor should be:
RESR > 1% (L / tOFF)
Stable operation requires the correct output filter
capacitor. When choosing the output capacitor, ensure
that:
COUT
tOFF
VOUT
× 79µFV / µs
In applications where the output is subject to large load
transients, the output capacitors size typically depends
on how much ESR is needed to prevent the output from
dipping too low under a load transient. Ignoring the sag
due to finite capacitance:
RESR ≤ ∆VOUT / IOUT(MAX)
The actual microfarad capacitance value required is
defined by the physical size needed to achieve low
ESR, and by the chemistry of the capacitor technology.
Thus, the capacitor is usually selected by ESR, size,
and voltage rating rather than by capacitance value
(this is true of tantalums, OS-CONs, and other elec-
trolytics). When using low-capacity filter capacitors
such as ceramic or polymer types, capacitor size is
usually determined by the capacity needed to prevent
VSAG and VSOAR from causing problems during load
transients. Generally, once enough capacitance is
added to meet the overshoot requirement, undershoot
at the rising-load edge is no longer a problem. The
amount of overshoot and undershoot due to stored
inductor energy can be calculated as:
VSOAR = L IOUT2 /(2 COUT VOUT)
VSAG = L IOUT2/[2 COUT (VIN - VOUT)]
Soft-Start
Soft-start allows a gradual increase of the internal current
limit to reduce input surge currents at startup and at exit
from shutdown. A timing capacitor, CSS, placed from SS
to GND sets the rate at which the internal current limit is
changed. Upon power-up, when the device comes out of
undervoltage lockout (2.6V typ) or after the SHDN pin is
pulled high, a 4µA constant current source charges the
soft-start capacitor and the voltage on SS increases.
When the voltage on SS is less than approximately 0.7V,
the current limit is set to zero. As the voltage increases
from 0.7V to approximately 1.8V, the current limit is
adjusted from 0V to the current-limit threshold (see the
Electrical Characteristics). The voltage across the soft-
start capacitor changes with time according to the
equation:
VSS
=
4µA ×
CSS
t
10 ______________________________________________________________________________________

Share Link: 

datasheetq.com  [ Privacy Policy ]Request Datasheet ] [ Contact Us ]