MAX1809 데이터 시트보기 (PDF) - Maxim Integrated

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MAX1809

3A, 1MHz, DDR Memory Termination Supply

Maxim Integrated 

3A, 1MHz, DDR Memory Termination Supply

LX

VDDQ

MAX1809

VEXTREF

EXTREF

FB

(1.1V ≤ VEXTREF ≤ VIN - 1.7V)

VOUT = VEXTREF

LX

MAX1809

EXTREF

FB

R2 = R1[(VOUT / VEXTREF) - 1]

VOUT

R2

R1

Figure 5. Adjusting the Output Voltage Using EXTREF

Figure 6. Adjusting the Output Voltage at FB

The output current limit during soft-start varies with

the voltage on the soft-start pin, SS, according to the

equation:

ILIM(SS) =

VSS − 0.7V

1.1V

× ILIMIT

where ILIMIT is the current-limit threshold from the

Electrical Characteristics. The constant-current source

stops charging once the voltage across the soft-start

capacitor reaches 1.8V.

Applications Information

Frequency Variation with Output Current

The operating frequency of the MAX1809 is determined

primarily by tOFF (set by RTOFF), VIN, and VOUT as

shown in the following formula:

( ( ) ) fSW

=

VIN −

tOFF VIN

VOUT − VPMOS

− VPMOS + VNMOS

However, as the output current increases, the voltage

drop across the NMOS and PMOS switches increases

and the voltage across the inductor decreases. This

causes the frequency to drop. Assuming RPMOS =

RNMOS, the change in frequency can be approximated

with the following formula:

( ) ∆fSW

=

∆IOUT × RPMOS

VIN × tOFF

where RPMOS is the resistance of the internal MOSFETs

(90mΩ typ).

Circuit Layout and Grounding

Good layout is necessary to achieve the MAX1809’s

intended output power level, high efficiency, and low

noise. Good layout includes the use of ground planes,

careful component placement, and correct routing of

traces using appropriate trace widths. The following

points are in order of decreasing importance:

1) Minimize switched-current and high-current ground

loops. Connect the input capacitor’s ground, the

output capacitor’s ground, and PGND close together.

Connect the resulting PGND plane to GND at only

one point.

2) Connect the input filter capacitor less than 5mm

away from IN. The connecting copper trace carries

large currents and must be at least 1mm wide,

preferably 2.5mm.

3) Place the LX node components as close together

and as near to the device as possible. This reduces

resistive and switching losses as well as noise.

4) Ground planes are essential for optimum perfor-

mance. In most applications, the circuit is located on

a multilayer board and full use of the four or more

layers is recommended. For heat dissipation, con-

nect the exposed backside pad of the QFN pack-

age to a large analog ground plane, preferably on a

surface of the board that receives good airflow. If

the ground plane is located on the top layer, make

use of the N.C. pins adjacent to GND to lower thermal

resistance to the ground plane. If the ground is

located elsewhere, use several vias to lower thermal

resistance. Typical applications use multiple ground

planes to minimize thermal resistance. Avoid large

AC currents through the analog ground plane.

Voltage Positioning

In applications where the load transients are extremely

fast (>10A/µs), the total output capacitance has to be

large enough to handle the VSAG and VSOAR require-

ments while keeping within the output tolerance limits.

Voltage positioning reduces the total amount of output

capacitance needed to meet a given transient

response requirement. With voltage positioning, the

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