MAX17409 데이터 시트보기 (PDF) - Maxim Integrated

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MAX17409

1-Phase Quick-PWM GPU Controller

Maxim Integrated 

1-Phase Quick-PWM GPU Controller

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1, VIN = 12V, VDD = VCC = 5V, SHDN = ILIM = VCC, SKIP = GNDS = PGND = GND, VFB = VCSP = VCSN = 1.05V;

G5–G0 set for 1.05V (G0–G5 = 100110); TA = 0°C to +85°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 3)

PARAMETER

BIAS CURRENTS

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

Quiescent Supply Current (VCC)

ICC

Measured at VCC, SKIP = 5V, FB forced

above the regulation point

1.5

3

mA

Quiescent Supply Current (VDD)

Shutdown Supply Current (VCC)

Shutdown Supply Current (VDD)

IDD

Measured at VDD, SKIP = 0V, FB forced

above the regulation point, TA = +25°C

Measured at VCC, SHDN = GND, TA = +25°C

Measured at VDD, SHDN = GND, TA = +25°C

0.02

1

µA

0.01

1

µA

0.01

1

µA

FAULT PROTECTION

Output Overvoltage Protection

Threshold

Skip mode after output reaches the

regulation voltage or PWM mode;

measured at FB with respect to unloaded

250

300

350

mV

output voltage

VOVP

Soft-start, soft-shutdown, skip mode, and

output have not reached the regulation

voltage; measured at FB

1.45 1.50 1.55

V

Minimum OVP threshold; measured at FB

0.8

Output Overvoltage Propagation

Delay

tOVP FB forced 25mV above trip threshold

10

µs

Output Undervoltage Protection

Threshold

VUVP

Measured at FB with respect to unloaded

output voltage

-450

-400

-350

mV

Output Undervoltage

Propagation Delay

tUVP FB forced 25mV below trip threshold

10

µs

PWRGD Startup Delay

Measured at startup from the time when

SHDN goes high

3

5

8

ms

PWRGD Threshold

Measured at FB Lower threshold, falling

with respect to edge (undervoltage)

-350

-300

-250

unloaded output

mV

voltage, 15mV Upper threshold, rising

hysteresis (typ) edge (overvoltage)

+150

+200

+250

PWRGD Transition Blanking

Time

PWRGD Delay

PWRGD Output Low Voltage

PWRGD Leakage Current

tBLANK

Measured from the time when FB reaches

the target voltage (Note 4) based on the

slew rate

FB forced 25mV outside the PWRGD trip

threshold s

ISINK = 3mA

High state, PWRGD forced to 5V

20

µs

10

µs

0.4

V

1

µA

VCC Undervoltage-Lockout

Threshold

VUVLO(VCC)

Rising edge, 50mV typical hysteresis,

controller disabled below this level

4.05 4.25 4.48

V

CSN Discharge Resistance

in UVLO

VCC = VDD = 4.0V

8

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