MAX4032 데이터 시트보기 (PDF) - Maxim Integrated
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MAX4032
Maxim Integrated
MAX4032 Datasheet PDF : 10 Pages
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5V, 6dB Video Buffer with Sync-Tip Clamp,
Output Sag Correction, and 150nA Shutdown Current
AC ELECTRICAL CHARACTERISTICS
(VCC = 5.0V, GND = 0V, COUT = CSAG = 22µF, CIN = 0.1µF, RIN = 75Ω to GND, RL = 150Ω to GND, SHDN = 5.0V, TA = +25°C,
unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
Small-Signal -3dB Bandwidth
BWSS VOUT = 100mVP-P
Large-Signal -3dB Bandwidth
BWLS VOUT = 2VP-P
Small-Signal 0.1dB Gain Flatness BW0.1dBSS VOUT = 100mVP-P
Large-Signal 0.1dB Gain Flatness BW0.1dBLS VOUT = 2VP-P
Slew Rate
SR
VOUT = 2V step
Settling Time to 0.1%
Power-Supply Rejection Ratio
tS
PSRR
VOUT = 2V step
f = 100kHz
Output Impedance
Differential Gain
ZOUT
DG
f = 5MHz
NTSC
Differential Phase
DP
NTSC
Group Delay
D/dT f = 3.58MHz or 4.43MHz
Peak Signal to RMS Noise
SNR VIN = 1VP-P, 10MHz BW
Droop
CIN = 0.1µF (Note 4)
SHDN Enable Time
tON
VIN = VCLP + 1V, SHDN = 5V, VOUT settled
to within 1% of the final voltage
TYP MAX UNITS
55
MHz
45
MHz
18
MHz
17
MHz
275
V/µs
25
ns
50
dB
2.5
Ω
0.4
%
0.6
Degrees
20
ns
65
dB
2
3
%
250
ns
SHDN Disable Time
tOFF
VIN = VCLP + 1V, SHDN = 0V, VOUT settled
to below 1% of the output voltage
50
ns
Note 2: All devices are 100% production tested at TA = +25°C. Specifications over temperature limits are guaranteed by design.
Note 3: Voltage gain (AV) is referenced to the clamp voltage, i.e., an input voltage of VIN = VCLP + VI would produce an output volt-
age of VOUT = VCLP + AV x VI.
Note 4: Droop is guaranteed by the input bias current specification.
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