MAX4044ESD 데이터 시트보기 (PDF) - Maxim Integrated

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MAX4044ESD

Single/Dual/Quad, Low-Cost, SOT23, Micropower Rail-to-Rail I/O Op Amps

Maxim Integrated 

Single/Dual/Quad, Low-Cost, SOT23,

Micropower, Rail-to-Rail I/O Op Amps

For example, a MAX4040 running from a single +2.4V

supply, operating at TA = +25°C, can source 240µA to

within 100mV of VCC and is capable of driving a 9.6kΩ

load resistor to VEE:

RL =

2.4V - 0.1V

240µA

= 9.6kΩ to VEE

The same application can drive a 4.6kΩ load resistor

when terminated in VCC / 2 (+1.2V in this case).

Driving Capacitive Loads

The MAX4040–MAX4044 are unity-gain stable for loads

up to 200pF (see Load Resistor vs. Capacitive Load

graph in Typical Operating Characteristics).

Applications that require greater capacitive drive capa-

bility should use an isolation resistor between the output

and the capacitive load (Figures 6a–6c). Note that this

alternative results in a loss of gain accuracy because

RISO forms a voltage divider with the load resistor.

Power-Supply Bypassing and Layout

The MAX4040–MAX4044 family operates from either a

single +2.4V to +5.5V supply or dual ±1.2V to ±2.75V

supplies. For single-supply operation, bypass the

power supply with a 100nF capacitor to VEE (in this

case GND). For dual-supply operation, both the VCC

and VEE supplies should be bypassed to ground with

separate 100nF capacitors.

Good PC board layout techniques optimize perfor-

mance by decreasing the amount of stray capacitance

at the op amp’s inputs and output. To decrease stray

capacitance, minimize trace lengths by placing exter-

nal components as close as possible to the op amp.

Surface-mount components are an excellent choice.

Using the MAX4040–MAX4044

as Comparators

Although optimized for use as operational amplifiers,

the MAX4040–MAX4044 can also be used as rail-to-rail

I/O comparators. Typical propagation delay depends

on the input overdrive voltage, as shown in Figure 7.

External hysteresis can be used to minimize the risk of

output oscillation. The positive feedback circuit, shown

in Figure 8, causes the input threshold to change when

the output voltage changes state. The two thresholds

create a hysteresis band that can be calculated by the

following equations:

VHYST = VHI - VLO

VLO = VIN x R2 / (R1 + (R1 x R2 / RHYST) + R2)

VHI = [(R2 / R1 x VIN) + (R2 / RHYST) x VCC] /

(1 + R1 / R2 + R2 / RHYST)

RISO

MAX4040–

RL

CL

MAX4044

AV =

RL

RL + RISO

≈

1

Figure 6a. Using a Resistor to Isolate a Capacitive Load from

the Op Amp

MAX4040/42/44 fig06b

50mV/div

IN

50mV/div

OUT

100µs/div

RISO = NONE, RL = 100kΩ, CL = 700pF

Figure 6b. Pulse Response without Isolating Resistor

MAX4040/42/44 fig06c

50mV/div

IN

50mV/div

OUT

100µs/div

RISO = 1kΩ, RL = 100kΩ, CL = 700pF

Figure 6c. Pulse Response with Isolating Resistor

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