MAX5064BATC(2005) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX5064BATC
(Rev.:2005)

125V/2A, High-Speed, Half-Bridge MOSFET Drivers

Maxim Integrated 

125V/2A, High-Speed,

Half-Bridge MOSFET Drivers

The voltage at BBM is regulated to 1.3V. The BBM circuit

adjusts tBBM depending on the current drawn by RBBM.

Bypass BBM to AGND with a 1nF or smaller ceramic

capacitor (CBBM) to avoid any effect of ground bounce

caused during switching. The charging time of CBBM

does not affect tBBM at turn-on because the BBM voltage

is stabilized before the UVLO clears the device turn-on.

Topologies like the two-switch forward converter, where

both high- and low-side switches are turned on and off

simultaneously, can have the BBM function disabled by

leaving BBM unconnected. When disabled, tBBM is typi-

cally 1ns.

Driver Logic Inputs (IN_H, IN_L, IN_H+,

IN_H-, IN_L+, IN_L-)

The MAX5062_/MAX5064A are CMOS (VDD / 2) logic-

input drivers while the MAX5063_/MAX5064B have TTL-

compatible logic inputs. The logic-input signals are

independent of VDD. For example, the IC can be pow-

ered by a 10V supply while the logic inputs are provid-

ed from a 12V CMOS logic. Also, the logic inputs are

protected against voltage spikes up to 15V, regardless

of the VDD voltage. The TTL and CMOS logic inputs

have 400mV and 1.6V hysteresis, respectively, to avoid

double pulsing during transition. The logic inputs are

high-impedance pins and should not be left floating.

The low 2.5pF input capacitance reduces loading and

increases switching speed. The noninverting inputs are

pulled down to GND and the inverting inputs are pulled

up to VDD internally using a 1MΩ resistor. The PWM

output from the controller must assume a proper state

while powering up the device. With the logic inputs

floating, the DH and DL outputs pull low as VDD rises

up above the UVLO threshold.

The MAX5064_ has two logic inputs per driver, which

provide greater flexibility in controlling the MOSFET.

Use IN_H+/IN_L+ for noninverting logic and IN_H-/

IN_L- for inverting logic operation. Connect

IN_H+/IN_L+ to VDD and IN_H-/IN_L- to GND if not

used. Alternatively, the unused input can be used as an

ON/OFF function. Use IN_+ for active-low and IN_- for

active-high shutdown logic.

Table 1. MAX5064_ Truth Table

IN_H+/IN_L+

Low

Low

High

High

IN_H-/IN_L-

Low

High

Low

High

DH/DL

Low

Low

High

Low

Applications Information

Supply Bypassing and Grounding

Pay extra attention to bypassing and grounding the

MAX5062/MAX5063/MAX5064. Peak supply and output

currents may exceed 4A when both drivers are driving

large external capacitive loads in-phase. Supply drops

and ground shifts create forms of negative feedback for

inverters and may degrade the delay and transition

times. Ground shifts due to insufficient device ground-

ing may also disturb other circuits sharing the same AC

ground return path. Any series inductance in the VDD,

DH, DL, and/or GND paths can cause oscillations due

to the very high di/dt when switching the MAX5062/

MAX5063/MAX5064 with any capacitive load. Place

one or more 0.1µF ceramic capacitors in parallel as

close to the device as possible to bypass VDD to GND

(MAX5062/MAX5063) or PGND (MAX5064). Use a

ground plane to minimize ground return resistance and

series inductance. Place the external MOSFET as close

as possible to the MAX5062/MAX5063/MAX5064 to fur-

ther minimize board inductance and AC path resis-

tance. For the MAX5064_ the low-power logic ground

(AGND) is separated from the high-power driver return

(PGND). Apply the logic-input signal between IN_ to

AGND and connect the load (MOSFET gate) between

DL and PGND.

Power Dissipation

Power dissipation in the MAX5062/MAX5063/MAX5064

is primarily due to power loss in the internal boost

diode and the nMOS and pMOS FETS.

For capacitive loads, the total power dissipation for the

device is:

( ) PD

=

⎛

⎝

CL

×

VDD2 ×

fSW

⎞

⎠

+

IDDO +

IBSTO

× VDD

where CL is the combined capacitive load at DH and

DL. VDD is the supply voltage and fSW is the switching

frequency of the converter. PD includes the power dis-

sipated in the internal bootstrap diode. The internal

power dissipation reduces by PDIODE, if an external

bootstrap Schottky diode is used. The power dissipa-

tion in the internal boost diode (when driving a capaci-

tive load) will be the charge through the diode per

switching period multiplied by the maximum diode for-

ward voltage drop (Vf = 1V).

( ) PDIODE = CDH × VDD − 1 × fSW × Vf

______________________________________________________________________________________ 11

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