MAX5064BATC(2005) 데이터 시트보기 (PDF) - Maxim Integrated

부품명

상세내역

제조사

MAX5064BATC
(Rev.:2005)

125V/2A, High-Speed, Half-Bridge MOSFET Drivers

Maxim Integrated 

125V/2A, High-Speed,

Half-Bridge MOSFET Drivers

MAX5062/MAX5063 Pin Description

PIN

NAME

FUNCTION

1

VDD

Power Input. Bypass to GND with a parallel combination of 0.1µF and 1µF ceramic capacitor.

2

BST

Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the

high-side MOSFET driver supply.

3

DH

High-Side-Gate Driver Output. Driver output for the high-side MOSFET gate.

4

HS

Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.

5

IN_H

High-Side Noninverting Logic Input

6

IN_L

Low-Side Noninverting Logic Input (MAX5062A/C, MAX5063A/C). Low-side inverting logic input

(MAX5062B/D, MAX5063B/D).

7

GND

Ground. Use GND as a return path to the DL driver output and IN_H/IN_L inputs.

8

DL

Low-Side-Gate Driver Output. Drives low-side MOSFET gate.

—

EP

Exposed Pad. Internally connected to GND. Externally connect the exposed pad to a large ground

plane to aid in heat dissipation (MAX5062C/D, MAX5063C/D only).

MAX5064 Pin Description

PIN

NAME

FUNCTION

1

BST

Boost Flying Capacitor Connection. Connect a 0.1µF ceramic capacitor between BST and HS for the

high-side MOSFET driver supply.

2

DH

High-Side-Gate Driver Output. Drives high-side MOSFET gate.

3

HS

Source Connection for High-Side MOSFET. Also serves as a return terminal for the high-side driver.

4

AGND

Analog Ground. Return path for low-switching current signals. IN_H/IN_L inputs referenced to

Break-Before-Make Programming Resistor Connection. Connect a 10kΩ to 100kΩ resistor from BBM

5

BBM

to AGND to program the break-before-make time (tBBM) from 16ns to 95ns. Resistance values

greater than 200kΩ disables the BBM function and makes tBBM = 1ns. Bypass this pin with at least a

1nF capacitor to AGND.

6

IN_H-

High-Side Inverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to

AGND when not used.

7

IN_H+

High-Side Noninverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to

VDD when not used.

8

IN_L-

Low-Side Inverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to AGND

when not used.

9

IN_L+

Low-Side Noninverting CMOS (VDD / 2) (MAX5064A), or TTL (MAX5064B) Logic Input. Connect to

VDD when not used.

10

PGND

Power Ground. Return path for high-switching current signals. Use PGND as a return path for the

low-side driver.

11

DL

Low-Side-Gate Driver Output. Drives the low-side MOSFET gate.

12

VDD

Power Input. Bypass to PGND with a 0.1µF ceramic in parallel with a 1µF ceramic capacitor.

—

EP

Exposed Pad. Internally connected to AGND. Externally connect to a large ground plane to aid in

heat dissipation.

8 _______________________________________________________________________________________

Share Link: