MAX5064AATC 데이터 시트보기 (PDF) - Maxim Integrated

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MAX5064AATC

125V/2A, High-Speed, Half-Bridge MOSFET Drivers

Maxim Integrated 

125V/2A, High-Speed,

Half-Bridge MOSFET Drivers

Topologies like the two-switch forward converter, where

both high- and low-side switches are turned on and off

simultaneously, can have the BBM function disabled by

leaving BBM unconnected. When disabled, tBBM is typi-

cally 1ns.

Driver Logic Inputs (IN_H, IN_L, IN_H+,

IN_H-, IN_L+, IN_L-)

The MAX5062_/MAX5064A are CMOS (VDD / 2) logic-

input drivers while the MAX5063_/MAX5064B have TTL-

compatible logic inputs. The logic-input signals are

independent of VDD. For example, the IC can be pow-

ered by a 10V supply while the logic inputs are provid-

ed from a 12V CMOS logic. Also, the logic inputs are

protected against voltage spikes up to 15V, regardless

of the VDD voltage. The TTL and CMOS logic inputs

have 400mV and 1.6V hysteresis, respectively, to avoid

double pulsing during transition. The logic inputs are

high-impedance pins and should not be left floating.

The low 2.5pF input capacitance reduces loading and

increases switching speed. The noninverting inputs are

pulled down to GND and the inverting inputs are pulled

up to VDD internally using a 1MΩ resistor. The PWM

output from the controller must assume a proper state

while powering up the device. With the logic inputs

floating, the DH and DL outputs pull low as VDD rises

up above the UVLO threshold.

The MAX5064_ has two logic inputs per driver, which

provide greater flexibility in controlling the MOSFET.

Use IN_H+/IN_L+ for noninverting logic and IN_H-/

IN_L- for inverting logic operation. Connect

IN_H+/IN_L+ to VDD and IN_H-/IN_L- to GND if not

used. Alternatively, the unused input can be used as an

ON/OFF function. Use IN_+ for active-low and IN_- for

active-high shutdown logic.

Table 1. MAX5064_ Truth Table

IN_H+/IN_L+

IN_H-/IN_L-

DH/DL

Low

Low

Low

Low

High

Low

High

Low

High

High

High

Low

shoot-through in the absence of external BBM delay

during the narrow pulse at low duty cycle (see Figure 2).

At high duty cycle (close to 100%) the DH minimum low

pulse width (tDmin-DH-L) must be higher than the DL

minimum low pulse width (tDmin-DL-L) to avoid overlap

and shoot-through (see Figure 3). In the case of

MAX5062/MAX5063/MAX5064, there is a possibility of

about 40ns overlap if an external BBM delay is not pro-

vided. We recommend adding external delay in the INH

path so that the minimum low pulse width seen at INH

is always longer than tPW-min. See the Electrical

Characteristics table for the typical values of tPW-MIN.

VDD

A)

VIN

PWMIN

INH

DH

N

VOUT

HS

INL

DL

N

MAX5062B/MAX5062D/MAX5063B/MAX5063D/MAX5064

B) PWMIN

tDMIN-DH-H

DH

Minimum Pulse Width

The MAX5062/MAX5063/MAX5064 uses a single-shot

level shifter architecture to achieve low propagation

delay. Typical level shifter architecture causes a mini-

mum (high or low) pulse width (tDmin) at the output that

may be higher than the logic-input pulse width. For

MAX5062/MAX5063/MAX5064 devices, the DH mini-

mum high pulse width (tDmin-DH-H) is lower than the DL

minimum low pulse width (tDmin-DL-L) to avoid any

BUILT-IN

DEAD TIME

DL

tDMIN-DL-L

Figure 2. Minimum Pulse-Width Behavior for Narrow Duty-

Cycle Input (On-Time < tPW_MIN)

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