APU0071-002WE-TY 데이터 시트보기 (PDF) - Anpec Electronics
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APU0071-002WE-TY Datasheet PDF : 28 Pages
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APU0071
PIN DESCRIPTION
PIN
Input /
Output
Name
Description
Interface
VDD
VSS (GND)
V2,V3,V5
S1 ~ S80
For logical circuit (+3v,+5v)
P
Power supply & LCD
Bias pin
0V (GND)
Bias voltage level for LCD driving
Output Segment output Segment signal output for LCD driving
Power
Supply
LCD
C1 ~ C16 Output Common output Common signal output for LCD driving
LCD
EXTCLK
EXT_INT
Input
Input
External clock Input
When using external clock, used as clock input pin.
When using internal oscillator, connect to VDD or VSS.
External / Internal When EXT_INT = “High”, external clock is used.
oscillator clock select When “Low”, instruction oscillator is used.
External
clock
MPU
Used as register selection input.
RS
Input Register select
When RS = “High”, data register is selected.
When RS = “Low”, instruction register is selected.
Used as read / write selection input.
R_NW
Input Read / Write
When RW = “High”, read operation.
When RW = “Low”, write operation.
E
Input Read / Write enable Used as read / write enable signal.
When 8-bit bus mode, used as low order bi-directional
DB0 ~ DB3
data bus.
MPU
During 4-bit bus mode open these pins.
Input /
Output
Data Bus 0 ~ 7
When 8-bit bus mode, used as high order bi-directional
data bus. In case of 4-bit bus mode, used as both high
DB4 ~ DB7
and low order.
DB7 is used for Busy Flag output during read
instruction operation.
EXT_RST Input Reset
If it is necessary to initialize the system by hardware,
force “Low”, level signal to this terminal about 1.2 ms.
OSC_TS Output Test Pin
Internal oscillator test pin. Open this pin.
POR_TS Output Test Pin
Internal test pin. Open this pin.
M_TS
Output Test Pin
Internal test pin. Open this pin.
CLK1_TS Output Test Pin
Internal test pin. Open this pin.
Copyright ANPEC Electronics Corp.
5
Rev. A.07 - FEB., 2002
www.anpec.com.tw
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