MAX6830 데이터 시트보기 (PDF) - Maxim Integrated
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MAX6830
Maxim Integrated
MAX6830 Datasheet PDF : 13 Pages
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MAX6826-MAX6831
Dual Ultra-Low-Voltage SOT23 µP Supervisors with
Manual Reset and Watchdog Timer
Electrical Characteristics (continued)
(VCC = +4.5V to +5.5V for MAX68_ _L/M, VCC = +2.7V to +3.6V for MAX68_ _T/S/R, VCC = +2.1V to +2.75V for MAX68_ _Z/Y,
VCC = +1.53V to +2.0V for MAX68_ _W/V; TA = -40°C to +125°C, unless otherwise specified. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
RESET Output HIGH
(Push-Pull Only)
Open-Drain RESET Output
Leakage Current (Note 1)
SYMBOL
CONDITIONS
MIN TYP
VCC ≥ 1.8V, ISOURCE = 200µA, reset not asserted 0.8 × VCC
VOH
VCC ≥ 3.15V, ISOURCE = 500µA, reset not asserted 0.8 × VCC
VCC ≥ 4.75V, ISOURCE = 800µA, reset not asserted 0.8 × VCC
ILKG RESET not asserted
MAX UNITS
V
1.0
µA
RESET Output HIGH
(Push-Pull Only)
RESET Output LOW
(Push-Pull Only)
MANUAL RESET INPUT
VOH
VOH
VCC ≥ 1.0V, ISOURCE = 1µA, reset asserted,
TA = 0°C to +85°C
VCC ≥ 1.50V, ISOURCE = 100µA, reset asserted
VCC ≥ 2.55V, ISOURCE = 500µA, reset asserted
VCC ≥ 4.25V, ISOURCE = 800µA, reset asserted
VCC ≥ 1.8V, ISINK = 500µA, reset asserted
VCC ≥ 3.15V, ISINK = 1.2mA, reset asserted
VCC ≥ 4.75V, ISINK = 3.2mA, reset asserted
0.8 × VCC
0.8 × VCC
0.8 × VCC
0.8 × VCC
V
0.3
0.3
V
0.3
MR Input voltage
VIL
VIH
MR Minimum Input Pulse
0.7 × VCC
1
0.3 × VCC V
µs
MR Glitch Rejection
100
ns
MR to Reset Delay
200
ns
MR Pullup Resistance
25
50
75
kΩ
WATCHDOG INPUT
Watchdog Timeout Period
WDI Pulse Width (Note 2)
WDI Input Voltage
WDI Input Current
tWD
tWDI
VIL
VIH
IWDI
TA = -40°C to +85°C
TA = -40°C to +125°C
WDI = VCC, time average
WDI = 0, time average
1.12 1.6
2.4
s
0.80
2.60
50
ns
0.7 × VCC
0.3 × VCC V
120 160
µA
-20
-15
Note 1: Over-temperature limits are guaranteed by design and not production tested. Devices tested at +25°C.
Note 2: Guaranteed by design and not production tested.
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