M50LPW116 데이터 시트보기 (PDF) - STMicroelectronics
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M50LPW116 Datasheet PDF : 36 Pages
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M50LPW116
Figure 2. Logic Diagram (A/A Mux Interface)
VCC VPP
11
A0-A10
8
DQ0-DQ7
RC
M50LPW116
IC
RB
G
W
RP
VSS
AI05468
Figure 3. TSOP Connections
DESCRIPTION
The M50LPW116 is a 16 Mbit (2Mb x8) non-
volatile memory that can be read, erased and
reprogrammed. These operations can be
performed using a single low voltage (3.0 to 3.6V)
supply. For fast programming, and fast erasing, an
optional 12V power supply can be used to reduce
the programming and the erasing times.
The memory is divided into blocks that can be
erased independently so it is possible to preserve
valid data while old data is erased. Blocks can be
protected individually (except Blocks 15 to 0,
which have global protection) to prevent
accidental Program or Erase commands from
modifying the memory. Program and Erase
commands are written to the Command Interface
of the memory. An on-chip Program/Erase
Controller simplifies the process of programming
or erasing the memory by taking care of all of the
special operations that are required to update the
memory contents. The end of a program or erase
operation can be detected and any error
conditions identified. The command set required
to control the memory is consistent with JEDEC
standards.
The M50LPW116 features an asymmetrical block
architecture. It has an array of 50 blocks: 1 Boot
Block of 16KBytes, 2 Parameter Blocks of
NC
IC (VIH)
NC
NC
NC
NC
A10
NC
RC
VCC
VPP
RP
NC
NC
A9
A8
A7
A6
A5
A4
NC
IC (VIL)
NC
NC
NC
NC
GPI4
NC
CLK
VCC
VPP
RP
NC
NC
GPI3
GPI2
GPI1
GPI0
WP
TBL
1
40
10
31
M50LPW116
11
30
20
21
VSS
VSS
VCC
VCC
LFRAME W
INIT
G
RFU
RB
RFU
DQ7
RFU
DQ6
RFU
DQ5
RFU
DQ4
VCC
VSS
VSS
LAD3
VCC
VSS
VSS
DQ3
LAD2 DQ2
LAD1 DQ1
LAD0 DQ0
ID0
A0
ID1
A1
ID2
A2
ID3
A3
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