MAX8833 데이터 시트보기 (PDF) - Maxim Integrated
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MAX8833 Datasheet PDF : 20 Pages
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Dual, 3A, 2MHz Step-Down Regulator
Pin Description
PIN
NAME
FUNCTION
Power-Good Open-Drain Output for Regulator 1. PWRGD1 is high impedance when VREFIN ≥ 0.54V and
1
PWRGD1 VFB1 ≥ 0.9 x VREFIN. PWRGD1 is low when VREFIN < 0.54V, EN1 is low, VDD or IN1 is below UVLO, the
thermal shutdown is activated, or when VFB1 < 0.9 x VREFIN.
External Reference Input for Regulator 1. Connect an external reference to REFIN, or connect REFIN to SS1
2
REFIN to use the internal reference. REFIN is discharged to GND through 335Ω when EN1 is low or regulator 1 is
shut down due to a fault condition.
3
VDD Supply Voltage. Connect a 10Ω resistor from VDD to VDL and connect a 0.1µF capacitor from VDD to GND.
4
GND
Analog Ground. Connect GND to the analog ground plane. Connect the analog and power ground planes
together at a single point near the IC.
5
N.C. No Connection
6
VDL Supply Voltage Input for Low-Side Gate Drive. Connect VDL to IN_ or the highest available supply voltage
less than 3.6V. Connect a 1µF capacitor from VDL to the power ground plane.
Frequency Set and Synchronization. Connect a 4.75kΩ to 20.5kΩ resistor from FSYNC to GND to set
7
FSYNC switching frequency or drive with a 250kHz to 2.5MHz clock signal to synchronize switching.
RFSYNC = (T - 0.05µs) x (10kΩ/0.95µs), where T is the oscillator period.
Power-Good Open-Drain Output for Regulator 2. PWRGD2 is high impedance when VSS2 ≥ 0.54V and VFB2
8
PWRGD2 ≥ 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V, EN2 is low, VDD or IN2 is below UVLO, the thermal
shutdown is activated, or when VFB2 < 0.9 x VSS2.
9
SS2
Soft-Start for Regulator 2. Connect a capacitor from SS2 to GND to set the soft-start time. See the Setting the Soft-
Start Time section. SS2 is internally pulled low with 335Ω when EN2 is low or regulator 2 is in a fault condition.
10
FB2 Feedback Input for Regulator 2. Connect FB2 to the center of an external resistor-divider from the output to
GND to set the output voltage from 0.6V to 90% of VIN2. FB2 is high impedance when the IC is shut down.
Compensation for Regulator 2. COMP2 is the output of the internal voltage-error amplifier. Connect external
11
COMP2 compensation network from COMP2 to FB2. See the Compensation Design section. COMP2 is internally
pulled to GND when the output is shut down.
12
13, 14
EN2 Enable Input for Regulator 2. Drive EN2 high to enable regulator 2, or drive low for shutdown. For always-on
operation, connect EN2 to VDD.
IN2
Power-Supply Input for Regulator 2. The voltage range is 2.35V to 3.6V. Connect two 10µF and one 0.1µF
ceramic capacitors from IN2 to PGND2.
15, 16, 17 PGND2 Power Ground for Regulator 2. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
18, 19
LX2
Inductor Connection for Regulator 2. Connect an inductor between LX2 and the regulator output. LX2 is high
impedance when the IC is shut down.
Bootstrap Connection for Regulator 2. Connect a 0.1µF capacitor from BST2 to LX2. BST2 is the supply for
20
BST2 the high-side gate drive. BST2 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX2 to BST2 and from VDL to BST2.
Bootstrap Connection for Regulator 1. Connect a 0.1µF capacitor from BST1 to LX1. BST1 is the supply for
21
BST1 the high-side gate drive. BST1 is charged from VDL with an internal pMOS switch. In shutdown, there is an
internal diode junction from LX1 to BST1 and from VDL to BST1.
22, 23
LX1
Inductor Connection for Regulator 1. Connect an inductor between LX1 and the regulator output. LX1 is high
impedance when the IC is shut down.
24, 25, 26 PGND1 Power Ground for Regulator 1. Connect all PGND_ pins to the power ground plane. Connect the power
ground and analog ground planes together at a single point near the IC.
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