MAX9526AEI(2010) 데이터 시트보기 (PDF) - Maxim Integrated

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MAX9526AEI
(Rev.:2010)

Low-Power, High-Performance NTSC/PAL Video Decoder

Maxim Integrated 

Low-Power, High-Performance

NTSC/PAL Video Decoder

XTAL/OSC

XTAL2

FROM AFE

10

SYNC

PROCESSING

OSCILLATOR

CLOCK

MUX

GENERATOR

MUX

AND PLL

NONSTD

VIDEO

CLOCK

Figure 2. Sync Processing, Clock Generation, and PLL

VREF Generation

A differential signal path is used to process the analog

video signal to minimize the effect of noise coupling. A

DC reference (VREF) of 850mV is internally generated

and decoupled externally with a 0.1µF capacitor.

Identical signal paths and video buffers are used for

both the selected video input and the video reference

voltage. The signals are converted to a fully differential

signal by the analog AGC circuit.

DC Restoration DAC

The video inputs, VIN1 and VIN2, are AC-coupled to the

MAX9526 with 0.1µF capacitors. The DC restoration cir-

cuit sets the sync level at the output of the ADC by sink-

ing or sourcing current at the selected video input. A

digital control at the ADC output is used to monitor the

average sync level. An error signal is generated in the

digital control block that is used by a current DAC to

source or sink current to the AC-coupled input to

restore the DC level. The DC restoration circuit also cor-

rects the offset in the analog signal chain and sets the

sync level at the ADC output to code 32 (decimal).

Analog Automatic Gain Control (Analog AGC)

The MAX9526 includes an analog variable-gain amplifi-

er with a digitally controlled gain for automatic gain

control (AGC). The AGC uses the sync amplitude at the

output of the ADC to control the gain. For signals with-

out copy protection, the AGC adjusts the gain until the

sync amplitude is 208 (decimal) codes at the ADC out-

put. For inputs with copy protection, the AGC automati-

cally compensates for the reduced sync amplitude on

active lines.

The analog AGC loop can be disabled and the gain is

set manually to 1 of 16 values using the Gain Control

register 0x0A. The range of analog gain is 3.5dB to

12dB.

Analog Lowpass Filter (LPF)

The MAX9526 includes a high-performance anti-aliasing

analog lowpass filter with a 3dB bandwidth of 13MHz

(typ) and better than 0.25dB (typ) passband flatness to

5MHz. This eliminates the need for external filtering on

the video inputs. The filter typically provides 36dB atten-

uation at 53MHz (1MHz below ADC sample rate).

54Msps Video ADC

A 10-bit, 54Msps ADC converts the filtered analog

composite video signal for digital signal processing

(composite video demodulation).

Digital Filtering

Digital filtering at the ADC output removes any out-of-

band interference and improves the signal-to-noise

ratio before decoding. The signal path includes a digi-

tal anti-aliasing lowpass filter that has 1dB of passband

flatness to 5.5MHz and a minimum of 45dB of stopband

attenuation for frequencies greater than 9MHz.

Sync Processing, Clock Generation,

and PLL

The sync processing, clock generation, and PLL extract

the timing information from incoming video and gener-

ate the clock for the rest of the chip. Figure 2 shows the

block diagram for this block.

Crystal Oscillator/Clock Input

The MAX9526 includes a low-jitter crystal oscillator cir-

cuit optimized for use with an external 27MHz crystal.

The device also accepts an external CMOS logic-level

clock at either 27MHz or 54MHz. To use an external

clock (27MHz or 54MHz) instead of a crystal, set

XTAL_DIS = 1 in register 0x0D. To use a 54MHz exter-

nal clock instead of a 27MHz clock, SEL_54MHz must

also be set to 1 in register 0x0D.

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