MC14LC5447DW 데이터 시트보기 (PDF) - Motorola => Freescale

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MC14LC5447DW

Calling Line Identification (CLID) Receiver with Ring Detector

Motorola => Freescale 

DESIGN INFORMATION

The circuit in Figure 2 illustrates in greater detail the rela-

tionship between Pins 3, 4, 6, and 7.

The external component values shown in Figure 2 are the

same as those shown in Figures 7 and 8. When VDD is

applied to the circuit in these two figures, the RC network will

charge cap C1 to VDD holding RT (Pin 6) off. If the PWRUP

(Pin 7) is also held at VDD, the MC14LC5447 will be in a

power–down mode, and will consume 1 µA of supply current

(max).

The resistor network (R2 – R4) attenuates the incoming

power ring applied to the top of R2. The values given have

been chosen to provide a sufficient voltage at RDI1 (Pin 3) to

turn on the Schmitt–trigger input with approximately a

40 Vrms or greater power ring input from tip and ring. When

VT+ of the Schmitt is exceeded, Q1 will be driven to satura-

tion discharging cap C1 on RT. This will initialize a partial

power–up, with only the portions of the part involved with the

ring signal analysis enabled, including RDI2 (Pin 4). At this

time the MC14LC5447 power consumption is increased to

approximately 2.4 mA (typ).

EXTERNAL

COMPONENTS

INTERNAL

COMPONENTS

R1

270 kΩ

VDD

C1

0.2 µF

470 kΩ

TO

BRIDGE R2

R3

18 kΩ

7

PWRUP

6

RT

Q1

3

RDI1

PWRUP

LOGIC

INTERNAL

POWER–

UP

R4

15 kΩ

4

RING

TO RDO

RDI2

ANALYSIS

PIN

CIRCUIT

Vref

1.2 V

Figure 2.

The value of R1 and C1 must be chosen to hold the RT pin

voltage below the VT+ of the RT Schmitt between the individ-

ual cycles of the power ring. The values shown will work for

ring frequencies of 15.3 Hz (min).

With RDI2 now enabled, a portion of the power ring above

1.2 V is fed to the ring analysis circuit. This circuit is a digital

integrator which looks at the duty cycle of the incoming sig-

nal. When the input to RDI2 is above 1.2 V, the integrator is

counting up at an 800 Hz rate. When the input to RDI2 falls

below 1.2 V, the integrator counts down at a 400 Hz rate.

3.5

VT+

3.25

3.0

VT–

2.75

2.5

2.25

2.0

1.75

1.5

1.25

1.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 6.5

VDD

Figure 3. VDD versus VT+ and VT–

A ring is qualified when an internal count of binary 48 is

reached. The ring is disqualified when the count drops to a

binary 32. The number of ring cycles required to qualify the

signal will depend on the amplitude of the voltage presented

to RDI2. The shortest amount of time needed to do the quali-

fication is approximately 60 ms. The shortest amount of time

required for dequalification will be approximately 40 ms.

Once the ring signal is qualified, the RDO pin will be sent

low. This can be fed back to PWRUP as shown in Figure 7, or

with a pull–up resistor, can be used as an interrupt to an

MCU as shown in Figure 8. In either case, once the PWRUP

pin is below VT–, the part will be fully powered up, and ready

to receive FSK. During this mode, the device current will in-

crease to approximately 6.2 mA (typ). The state of the RT pin

is now a “don’t care” as far as the part is concerned. Normal-

ly, however, this pin will be allowed to return to VDD.

After the FSK message has been received, the PWRUP

pin can be allowed to return to VDD and the part will return to

the standby mode, consuming less than 1 µA of supply cur-

rent. The part is now ready to repeat the same sequence for

the next incoming message.

TYPICAL DEMODULATOR PERFORMANCE

The following describes the performance of the

MC14LC5447 demodulator in the presence of noise over a

simulated Bell 3002 telephone loop.

The Bell 3002 loop represents a worst case local tele-

phone loop in North America. The characteristics of this loop,

which affect performance, are high frequency attenuation

and Envelope Delay Distortion (EDD) or group delay.

The minimum receiver sensitivity of the MC14LC5447 un-

der these conditions is typically – 45 dBm.

The MC14LC5447 achieves a Bit Error Rate (BER) of 1 ×

10–5 at a Signal–to–Noise Ratio (SNR) of 15 dB in V.23 op-

eration and at an SNR of 18 dB in Bell 202 operation (see

Figures 4 and 5).

All measurements in dBm are referenced to 600 Ω: 0 dBm

= 0.7746 Vrms.

All measurements were taken using the MC145460EVK

evaluation board.

MC14LC5447

6

MOTOROLA

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