MC68HC812A4CPV8E 데이터 시트보기 (PDF) - Freescale Semiconductor
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MC68HC812A4CPV8E
Freescale Semiconductor
MC68HC812A4CPV8E Datasheet PDF : 242 Pages
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Revision History
Revision History
Date
August,
2001
(Continued)
September,
2001
August,
2002
May,
2006
Revision
Level
4
5
6
7
Description
12.11.3 Data Direction Register for Timer Port — Repetitive information
removed. See 12.11.2 Timer Port Data Direction Register
18.12 Control Timing — Minimum values added for PWIRQ and PWTIM
18.14 Non-Multiplexed Expansion Bus Timing — Table heading changed to
reflect minimum and maximum values at 8 MHz
Table 12-3. Prescaler Selection — Added value column and updated prescale
factors
18.11 EEPROM Characteristics — Corrected minimum and maximum values
for programming and erase times
Figure 1-3. Expanded Wide Mode SRAM Expansion Schematic — On sheet
1 of this schematic removed reference to resistor R2
Figure 1-4. Expanded Narrow Mode SRAM Expansion Schematic — On
sheet 1 of this schematic removed reference to resistor R2
4.6.2 External Reset — Corrected reference to eight E-clock cycles to nine
E-clock cycles
Updated to meet Freescale identity guidelines.
1.3 Ordering Information — Updated Table 1-1. Ordering Information and
added Figure 1-1. Device Numbering System.
Figure 1-4. Expanded Wide Mode SRAM Expansion Schematic (Sheet 1 of 3)
— Updated sheet 1 and corrected title for sheets 2 and 3.
Figure 1-5. Expanded Narrow Mode SRAM Expansion Schematic (Sheet 1 of 3)
— Updated sheet 1 and corrected title for sheets 2 and 3.
Figure 3-9. Condition Code Register (CCR) — Corrected reset state for bit 7.
Table 4-1. Interrupt Vector Map — Corrected reference to clock monitor reset.
4.5 Resets — Reworked paragraph for clarity.
Figure 5-1. Mode Register (MODE) — Changed reset state designator from
Peripheral to Special peripheral.
Figure 10-3. Clock Function Register Map — Removed reference to Special
Reset for the COP Control Register.
Figure 10-9. COP Control Register (COPCTL) — Corrected reset states.
12.4.1 Prescaler — Corrected number of prescaler divides.
Figure 12-17. Timer Mask 2 Register (TMSK2) — Corrected reset state for bit 4.
Table 16-5. ATD Interrupt Sources — Corrected table title.
18.2 Functional Operating Range — Corrected operating temperature range
entries.
18.10 EEPROM Characteristics — Corrected minimum value for minimum
programming clock frequency.
18.11 Control Timing — Corrected maximum value for frequency of operation.
18.12 Peripheral Port Timing — Corrected table heading.
19.2 Package Dimensions — Replaced package dimension drawing with the
latest available.
Page
Number(s)
209
329
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197
328
40
42
77
Throughout
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46
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58
102
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237
MC68HC812A4 Data Sheet, Rev. 7
4
Freescale Semiconductor
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