MPC5534MVF66 데이터 시트보기 (PDF) - Freescale Semiconductor

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MPC5534MVF66

Microcontroller

Freescale Semiconductor 

Electrical Characteristics

Although there is no power sequencing required between VRC33 and VDDSYN during power up, for the

VRC stage turn-on to operate within specification, VRC33 must not lead VDDSYN by more than 600 mV

or lag by more than 100 mV. Higher spikes in the emitter current of the pass transistor will occur if VRC33

leads or lags VDDSYN by more than these amounts. The value of that higher spike in current depends on

the board power supply circuitry and the amount of board level capacitance.

Furthermore, when all of the PORs negate, the system clock will start to toggle, adding another large

increase of the current consumption from VRC33. If VRC33 lags VDDSYN by more than 100 mV, this

increased current consumption can drop VDD low enough to assert the 1.5-V POR again. Oscillations are

even possible because when the 1.5-V POR asserts, the system clock stops, causing the voltage on VDD

to rise until the 1.5-V POR negates again. Any oscillations stop when VRC33 is powered sufficiently.

When powering down, VRC33 and VDDSYN do not have a delta requirement to each other, because the

bypass capacitors internal and external to the device are already charged.

When not powering up or down, VRC33 and VDDSYN do not have a delta requirement to each other for

the VRC to operate within specification.

Although there are no power up/down sequencing requirements to prevent issues like latch-up, excessive

current spikes, etc., the state of the I/O pins during power up/down varies depending on power. Table 7

gives the pin state for the sequence cases for all pins with pad type pad_fc (fast type), and Table 8 for all

pins with pad type pad_mh (medium type) and pad_sh (slow type).

VDDE

LOW

VDDE

VDDE

VDDE

VDDEH

LOW

VDDEH

VDDEH

VDD33

X

LOW

VDD33

VDD33

Table 7. Power Sequence Pin States (Fast Pads)

VDD

X

X

LOW

VDD

pad_fc (Fast)

Output Driver

State

Low

High

High Impedance

Functional

Comment

Functional I/O pins are clamped to VSS and VDDE

POR asserted.

No POR asserted

VDD

X

LOW

VDD

Table 8. Power Sequence Pin States (Medium and Slow Pads)

pad_mh/pad_sh

(Medium and Slow)

Output Driver

Low

High Impedance

Functional

Comment

Functional I/O pins are clamped to VSS and VDDEH

POR asserted

No POR asserted

3.7.1 Power Up Sequence (If VRC33 Grounded)

In this case, the 1.5-V VDD supply must rise to 1.35-V before the 3.3-V VDDSYN and the RESET power

supplies rises above 2.0 V. This ensures that digital logic in the PLL on the 1.5-V supply will not begin to

operate below the specified operation range lower limit of 1.35 V. Since the internal 1.5-V POR is disabled,

MPC5534 Microcontroller Data Sheet, Rev. 0

Freescale Semiconductor

Preliminary—Subject to Change Without Notice

11

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