MPC5534MVZ80 데이터 시트보기 (PDF) - Freescale Semiconductor

부품명

상세내역

제조사

MPC5534MVZ80

Microcontroller

Freescale Semiconductor 

Electrical Characteristics

Table 12. HiP7 FMPLL Electrical Specifications (continued)

(VDDSYN = 3.0V to 3.6 V, VSS = VSSSYN = 0 V, TA = TL to TH)

Num

Characteristic

Symbol

Min.

Value

Max.

Value

Unit

20 Frequency Modulation Range Limit 14

Cmod

0.8

(fsysMax must not be exceeded)

21 ICO Frequency.

fico

48

fico=[fref*(MFD+4)]/(PREDIV+1) 15

2.4

80 16

%fsys

MHz

22 Predivider Output Frequency (to PLL)

fPREDIV

4

fMAX

MHz

1 All internal registers retain data at 0 Hz.

2 Up to the maximum frequency rating of the device (see Table 1).

3 “Loss of Reference Frequency” is the reference frequency detected internally, which transitions the PLL into self clocked mode.

4 Self clocked mode (SCM) frequency is the frequency that the PLL operates at when the reference frequency falls below fLOR.

This frequency is measured on the CLKOUT pin with the divider set to divide-by-2 of the system clock. NOTE: In SCM, the

MFD and PREDIV have no effect and the RFD is bypassed.

5 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,

Vextal – Vxtal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock.

6 This parameter is meant for those who do not use quartz crystals or resonators, but CAN osc, in crystal mode. In that case,

Vxtal – Vextal >= 400mV criteria has to be met for oscillator’s comparator to produce output clock.

7 Ixtal is the oscillator bias current out of the XTAL pin with both EXTAL and XTAL pins grounded.

8 CPCB_EXTAL and CPCB_XTAL are the measured PCB stray capacitances on EXTAL and XTAL, respectively

9 This specification applies to the period required for the PLL to relock after changing the MFD frequency control bits in the

synthesizer control register (SYNCR). From power up with crystal oscillator reference, the lock time will also include the crystal

startup time.

10 PLL is operating in 1:1 PLL mode.

11 VDDE = 3.0 to 3.6V

12 Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fsys.

Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise

injected into the PLL circuitry via VDDSYN and VSSSYN and variation in crystal oscillator frequency increase the jitter percentage

for a given interval. CLKOUT divider set to divide-by-2.

13 Values are with frequency modulation disabled. If frequency modulation is enabled, jitter is the sum of jitter + Cmod.

14 Modulation depth selected must not result in fsys value greater than the fsys maximum specified value.

15 fsys = fico / (2RFD)

16 Note that the ICO frequency may be higher than the maximum allowable system frequency, in that case, the FMPLL

Synthesizer Control Register Reduced Frequency Divider (FMPLL_SYNCR[RFD]) must be set to divide by 2 (RFD=0b001). In

other words, for a 40 MHz maximum device (system frequency), the FMPLL should be programmed to generate 80 MHz at the

ICO output and then divided by 2 by the RFD to provide the 40 MHz system clock.

3.10 eQADC Electrical Characteristics

Table 13. eQADC Conversion Specifications (Operating)

Num

Characteristic

1 ADC Clock (ADCLK) Frequency1

2 Conversion Cycles

Differential

Single Ended

3 Stop Mode Recovery Time2

Symbol

FADCLK

CC

TSR

Min

Max

1

12

13+2 (or 15)

14+2 (or 16)

10

13+128 (or 141)

14+128 (or 142)

—

Unit

MHz

ADCLK

cycles

µs

MPC5534 Microcontroller Data Sheet, Rev. 0

20

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

Share Link: