T35L6432A 데이터 시트보기 (PDF) - Taiwan Memory Technology
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T35L6432A Datasheet PDF : 15 Pages
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tm TE
CH
T35L6432A
TRUTH TABLE
OPERATION
ADDRESS CE CE2 CE2 ZZ ADSP ADSC ADV WRITE OE CLK DQ
USED
Deselected Cycle, Power Down None H X X L X
L
X
X X L-H High-Z
Deselected Cycle, Power Down None L X L L L X X
X X L-H High-Z
Deselected Cycle, Power Down None L H X L L X X
X X L-H High-Z
Deselected Cycle, Power Down None L X L L H L X
X X L-H High-Z
Deselected Cycle, Power Down None L H X L H L X
X X L-H High-Z
Snooze Cycle, Power Down
None X X X H X
X
X
X X X High-Z
READ Cycle, Begin Burst External L L H L L X X
X L L-H Q
READ Cycle, Begin Burst External L L H L L X X
X H L-H High-Z
WRITE Cycle, Begin Burst External L L H L H L X
L X L-H D
READ Cycle, Begin Burst External L L H L H L X
H L L-H Q
READ Cycle, Begin Burst External L L H L H L X
H H L-H High-Z
READ Cycle, Continue Burst Next X X X L H
H
L
H L L-H Q
READ Cycle, Continue Burst Next X X X L H
H
L
H H L-H High-Z
READ Cycle, Continue Burst Next H X X L X
H
L
H L L-H Q
READ Cycle, Continue Burst Next H X X L X
H
L
H H L-H High-Z
WRITE Cycle, Continue
Burst
Next X X X L H
H
L
L X L-H D
WRITE Cycle, Continue
Burst
Next H X X L X
H
L
L X L-H D
READ Cycle, Suspend Burst Current X X X L H H H
H L L-H Q
READ Cycle, Suspend Burst Current X X X L H H H
H H L-H High-Z
READ Cycle, Suspend Burst Current H X X L X H H
H L L-H Q
READ Cycle, Suspend Burst Current H X X L X H H
H H L-H High-Z
WRITE Cycle, Suspend Burst Current X X X L H H H
L X L-H D
WRITE Cycle, Suspend Burst Current H X X L X H H
L X L-H D
Note:
1. X means "don't care." H means logic HIGH. L means logic LOW. WRITE = L means any one or
more byte write enable signals (BW1, BW2 , BW3 or BW4 ) and BWE are LOW, or GW
equals LOW. WRITE = H means all byte write signal are HIGH.
2. BW1= enables write to DQ1-DQ8. BW2 = enables write to DQ9-DQ16. BW3 = enables write to
DQ17-DQ24. BW4 =enables write to DQ25-DQ32.
3. All inputs except OE must meet setup and hold times around the rising edge ( LOW to HIGH)
of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation. OE must be HIGH before the input data
required setup time plus High-Z time for OE and staying HIGH throughout the input data hold
time.
6. This device contains circuitry that will ensure the outputs will be High-Z during power-up.
7. ADSP= LOW along with chip being selected always initiates an internal READ cycle at the L-H
edge of CLK. A WRITE cycle can be performed by setting WRITE LOW for the CLK L-H edge
of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
Taiwan Memory Technology, Inc. reserves the right P. 6
to change products or specifications without notice.
Publication Date: DEC. 1998
Revision:A
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