MT48LC32M8A2TG-6ALD PDF VIEW DOWNLOAD, MT48LC32M8A2TG-6ALD 데이터시트

MT48LC32M8A2TG-6ALD(2007) 데이터 시트보기 (PDF) - Micron Technology

부품명

상세내역

제조사

MT48LC32M8A2TG-6ALD
(Rev.:2007)

256Mb: x4, x8, x16 SDRAM F

Micron Technology

MT48LC32M8A2TG-6ALD Datasheet PDF : 77 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

256Mb: x4, x8, x16 SDRAM

General Description

Table 3:

256Mb SDRAM Part Numbers

Notes:

Part Numbers

Architecture

MT48LC64M4A2TG

MT48LC64M4A2P

MT48LC64M4A2FB1

MT48LC64M4A2BB1

MT48LC32M8A2TG

MT48LC32M8A2P

MT48LC32M8A2FB1

MT48LC32M8A2BB1

MT48LC16M16A2TG

MT48LC16M16A2P

MT48LC16M16A2FG

MT48LC16M16A2BG

64 Meg x 4

32 Meg x 8

16 Meg x 16

1. Actual FBGA part marking shown on pages 76 and 77.

Package

54-pin TSOP II

60-ball FBGA

54-pin TSOP II

60-ball FBGA

54-pin TSOP II

54-ball FBGA

General Description

The 256Mb SDRAM is a high-speed CMOS, dynamic random-access memory containing

268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous

interface (all signals are registered on the positive edge of the clock signal, CLK). Each of

the x4’s 67,108,864-bit banks is organized as 8,192 rows by 2,048 columns by 4 bits. Each

of the x8’s 67,108,864-bit banks is organized as 8,192 rows by 1,024 columns by 8 bits.

Each of the x16’s 67,108,864-bit banks is organized as 8,192 rows by 512 columns by 16

bits.

Read and write accesses to the SDRAM are burst oriented; accesses start at a selected

location and continue for a programmed number of locations in a programmed

sequence. Accesses begin with the registration of an ACTIVE command, which is then

followed by a READ or WRITE command. The address bits registered coincident with the

ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select

the bank; A0–A12 select the row). The address bits registered coincident with the READ

or WRITE command are used to select the starting column location for the burst access.

The SDRAM provides for programmable read or write burst lengths (BL) of 1, 2, 4, or 8

locations, or the full page, with a burst terminate option. An auto precharge function

may be enabled to provide a self-timed row precharge that is initiated at the end of the

burst sequence.

The 256Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-

tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also

allows the column address to be changed on every clock cycle to achieve a high-speed,

fully random access. Precharging one bank while accessing one of the other three banks

will hide the PRECHARGE cycles and provide seamless, high-speed, random-access

operation.

The 256Mb SDRAM is designed to operate in 3.3V memory systems. An auto refresh

mode is provided, along with a power-saving, power-down mode. All inputs and outputs

are LVTTL-compatible.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8

256MSDRAM_2.fm - Rev. L 10/07 EN

Micron Technology, Inc., reserves the right to change products or specifications without notice.

Share Link: