MT48LC32M8A2P(2005) 데이터 시트보기 (PDF) - Micron Technology

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MT48LC32M8A2P
(Rev.:2005)

256Mb: x4, x8, x16 SDRAM

Micron Technology 

256Mb: x4, x8, x16

SDRAM

Table 6: Ball Descriptions (60-ball FBGA)

60-BALL FBGA

SYMBOL TYPE

DESCRIPTION

K2

L2

L8

J8, K7, J7

J2

M8, M7

N7, P8, P7, R8, R1, P2, P1,

N2, N1, M2, N8, M1, L1

C7, F7, F2, C2

A8, C7, D8, F7, F2, D1, C2,

A1

A1, A8, B1, B8, D1, D2, D7,

D8, E1, E8, G1, G2, G7,

G8, H1, H8, J1, K1, K8, L7

B1, B8, D2, D7, E1, E8, G1,

G2, G7, G8, H1, H8, J1, K1,

K8, L7

B7, C1, E7, F1

CLK

CKE

CS#

CAS#, RAS#,

WE#

DQM,

BA0, BA1

A0–A12

DQ0–DQ3

DQ0–DQ7

NC

NC

VDDQ

Input

Input

Input

Input

Input

Input

Input

(x4) I/O

(x8) I/O

x4

x8

Supply

Clock: CLK is driven by the system clock. All SDRAM input signals are sampled

on the positive edge of CLK. CLK also increments the internal burst counter

and controls the output registers.

Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal.

Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH

operation (all banks idle), ACTIVE POWER-DOWN (row active in any bank) or

CLOCK SUSPEND operation (burst/access in progress). CKE is synchronous except

after the device enters power-down and self refresh modes, where CKE

becomes asynchronous until after exiting the same mode. The input buffers,

including CLK, are disabled during power-down and self refresh modes,

providing low standby power. CKE may be tied HIGH.

Chip Select: CS# enables (registered LOW) and disables (registered HIGH) the

command decoder. All commands are masked when CS# is registered HIGH. CS#

provides for external bank selection on systems with multiple banks. CS# is

considered part of the command code.

Command Inputs: CAS#, RAS#, and WE# (along with CS#) define the

command being entered.

Input/Output Mask: DQM is sampled HIGH and is an input mask signal for

write accesses and an output enable signal for read accesses. Input data is

masked during a WRITE cycle. The output buffers are placed in a High-Z state

(two-clock latency) when during a READ cycle.

Bank Address Input(s): BA0 and BA1 define to which bank the ACTIVE, READ,

WRITE or PRECHARGE command is being applied. These pins also provide the

op-code during a LOAD MODE REGISTER command

Address Inputs: A0–A11 are sampled during the ACTIVE command (row-

address A0–A11) and READ/WRITE command (column-address A0–A8; with A10

defining auto precharge) to select one location out of the memory array in the

respective bank. A10 is sampled during a PRECHARGE command to determine if

all banks are to be precharged (A10 HIGH) or bank selected by BA0, BA1 (LOW).

The address inputs also provide the op-code during a LOAD MODE REGISTER

command.

Data Input/Output: Data bus

Data Input/Output: Data bus

No Connect: These pins should be left unconnected.

G1 is a no connect for this part but may be used as A12 in future designs.

No Connect: These pins should be left unconnected.

G1 is a no connect for this part but may be used as A12 in future designs.

DQ Power: Isolated power to DQs for improved noise immunity.

B2, C8, E2, F8

A7, R7

VSSQ

VDD

Supply DQ Ground: Isolated ground to DQs for improved noise immunity.

Supply Power Supply: Voltage dependant on option.

A2, H2, R2

VSS

Supply Ground.

PDF: 09005aef8091e6d1/Source: 09005aef8091e6a8

256MSDRAM.pmd – Rev. H; Pub. 2/05

11

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc. All rights reserved.

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