MT48LC32M8A2FB-7EL 데이터 시트보기 (PDF) - Micron Technology

부품명

상세내역

제조사

MT48LC32M8A2FB-7EL

256Mb: x4, x8, x16 SDRAM

Micron Technology 

256Mb: x4, x8, x16 SDRAM

Features

List of Figures

Figure 1: 64 Meg x 4 Functional Block Diagram ................................................................................................. 8

Figure 2: 32 Meg x 8 Functional Block Diagram ................................................................................................. 9

Figure 3: 16 Meg x 16 Functional Block Diagram ............................................................................................. 10

Figure 4: 54-Pin TSOP (Top View) .................................................................................................................. 11

Figure 5: 60-Ball FBGA (Top View) ................................................................................................................. 12

Figure 6: 54-Ball VFBGA (Top View) ............................................................................................................... 13

Figure 7: 54-Pin Plastic TSOP "TG/P" (400 mil) ............................................................................................... 15

Figure 8: 60-Ball FBGA "FB/BB" (8mm x 16mm) (x4, x8) .................................................................................. 16

Figure 9: 54-Ball VFBGA "BG/FG" (8mm x 14mm) (x16) .................................................................................. 17

Figure 10: 54-Ball VFBGA "B4/F4" (8mm x 8mm) (x16) ................................................................................... 18

Figure 11: Example: Temperature Test Point Location, 54-Pin TSOP (Top View) ............................................... 21

Figure 12: Example: Temperature Test Point Location, 54-Ball VFBGA (Top View) ............................................ 21

Figure 13: Example: Temperature Test Point Location, 60-Ball FBGA (Top View) .............................................. 22

Figure 14: ACTIVE Command ........................................................................................................................ 32

Figure 15: READ Command ........................................................................................................................... 33

Figure 16: WRITE Command ......................................................................................................................... 34

Figure 17: PRECHARGE Command ................................................................................................................ 35

Figure 18: Initialize and Load Mode Register .................................................................................................. 43

Figure 19: Mode Register Definition ............................................................................................................... 45

Figure 20: CAS Latency .................................................................................................................................. 48

Figure 21: Example: Meeting tRCD (MIN) When 2 < tRCD (MIN)/tCK < 3 .......................................................... 49

Figure 22: Consecutive READ Bursts .............................................................................................................. 51

Figure 23: Random READ Accesses ................................................................................................................ 52

Figure 24: READ-to-WRITE ............................................................................................................................ 53

Figure 25: READ-to-WRITE With Extra Clock Cycle ......................................................................................... 54

Figure 26: READ-to-PRECHARGE .................................................................................................................. 54

Figure 27: Terminating a READ Burst ............................................................................................................. 55

Figure 28: Alternating Bank Read Accesses ..................................................................................................... 56

Figure 29: READ Continuous Page Burst ......................................................................................................... 57

Figure 30: READ – DQM Operation ................................................................................................................ 58

Figure 31: WRITE Burst ................................................................................................................................. 59

Figure 32: WRITE-to-WRITE .......................................................................................................................... 60

Figure 33: Random WRITE Cycles .................................................................................................................. 61

Figure 34: WRITE-to-READ ............................................................................................................................ 61

Figure 35: WRITE-to-PRECHARGE ................................................................................................................. 62

Figure 36: Terminating a WRITE Burst ............................................................................................................ 63

Figure 37: Alternating Bank Write Accesses ..................................................................................................... 64

Figure 38: WRITE – Continuous Page Burst ..................................................................................................... 65

Figure 39: WRITE – DQM Operation ............................................................................................................... 66

Figure 40: READ With Auto Precharge Interrupted by a READ ......................................................................... 68

Figure 41: READ With Auto Precharge Interrupted by a WRITE ........................................................................ 69

Figure 42: READ With Auto Precharge ............................................................................................................ 70

Figure 43: READ Without Auto Precharge ....................................................................................................... 71

Figure 44: Single READ With Auto Precharge .................................................................................................. 72

Figure 45: Single READ Without Auto Precharge ............................................................................................. 73

Figure 46: WRITE With Auto Precharge Interrupted by a READ ........................................................................ 74

Figure 47: WRITE With Auto Precharge Interrupted by a WRITE ...................................................................... 74

Figure 48: WRITE With Auto Precharge ........................................................................................................... 75

Figure 49: WRITE Without Auto Precharge ..................................................................................................... 76

Figure 50: Single WRITE With Auto Precharge ................................................................................................. 77

PDF: 09005aef8091e6d1

256Mb_sdr.pdf - Rev. S 12/12 EN

4

Micron Technology, Inc. reserves the right to change products or specifications without notice.

© 1999 Micron Technology, Inc. All rights reserved.

Share Link: