74ABT16245BDL 데이터 시트보기 (PDF) - Philips Electronics
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74ABT16245BDL Datasheet PDF : 11 Pages
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Philips Semiconductors
16-bit bus transceiver (3-State)
Product specification
74ABT16245B
74ABTH16245B
DC ELECTRICAL CHARACTERISTICS
LIMITS
SYMBOL
PARAMETER
TEST CONDITIONS
Tamb = +25°C
Tamb = –40°C
to +85°C
UNIT
Min Typ Max Min Max
VIK
Input clamp voltage
VOH High-level output voltage
VOL Low-level output voltage
II
Input leakage current
VCC = 4.5V; IIK = –18mA
VCC = 4.5V; IOH = –3mA; VI = VIL or VIH
VCC = 5.0V; IOH = –3mA; VI = VIL or VIH
VCC = 4.5V; IOH = –32mA; VI = VIL or VIH
VCC = 4.5V; IOL = 64mA; VI = VIL or VIH
VCC = 5.5V; VI = GND or 5.5V
Control
pins
–0.9 –1.2
–1.2 V
2.5 2.9
2.5
V
3.0 3.4
3.0
V
2.0 2.4
2.0
V
0.42 0.55
0.55 V
±0.01 ±1.0
±1.0 µA
IHOLD
Bus hold current
A and B inputs
74ABTH16245B
IOFF Power-off leakage current
VCC = 4.5V; VI = 0.8V
VCC = 5.5V; VI = 2.0V
VCC = 5.5V; VI = 0 to 5.5V
VCC = 0.0V; VO or VI ≤ 4.5V
50
50
–75
–75
µA
±500
±5.0 ±100
±100 µA
IPU/IPD
Power-up/down 3-State
output current
VCC = 2.0V; VO = 0.5V; VI = GND or VCC;
VOE = Don’t care
±5.0 ±50
±50 µA
IIH+IOZH 3-State output High current VCC = 5.5V; VO = 5.5V; VI = VIL or VIH
0.1 10
10
µA
IIL+IOZL 3-State output Low current VCC = 5.5V; VO = 0.0V; VI = VIL or VIH
0.1 10
10
µA
ICEX
IO
Output high leakage current
Output current1
VCC = 5.5V; VO = 5.5V; VI = GND or VCC
VCC = 5.5V; VO = 2.5V
5.0 50
50
µA
–50 –92 –180 –50 –180 mA
ICCH
VCC = 5.5V; Outputs High, VI = GND or VCC
0.30 0.70
0.70 mA
ICCL Quiescent supply current
VCC = 5.5V; Outputs Low, VI = GND or VCC
10
19
19 mA
ICCZ
VCC = 5.5V; Outputs 3-State;
VI = GND or VCC
0.30 0.70
0.70 mA
Outputs enabled, one data input at 3.4V,
other inputs at VCC or GND; VCC = 5.5V
400 700
700 µA
∆ICC
Additional supply current per
input pin2
Outputs disabled, one data input at 3.4V,
other inputs at VCC or GND; VCC = 5.5V
100 250
Control pins, outputs disabled, one enable
input at 3.4V, other inputs at VCC or GND;
VCC = 5.5V
400 700
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. This is the bus hold overdrive current required to force the input to the opposite logic state.
250 µA
700 µA
1998 Feb 25
5
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