OR4E10 데이터 시트보기 (PDF) - Agere -> LSI Corporation
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OR4E10 Datasheet PDF : 124 Pages
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ORCA Series 4 FPGAs
Preliminary Data Sheet
December 2000
Programmable Logic Cells (continued)
F5D
K7_0
K7_1
K7_2
K7_3
K6_0
K6_1
K6_2
K6_3
K5_0
K5_1
K5_2
K5_3
K4_0
K4_1
K4_2
K4_3
F5C
F5B
K3_0
K3_1
K3_2
K3_3
K2_0
K2_1
K2_2
K2_3
K1_0
K1_1
K1_2
K1_3
K0_0
K0_1
K0_2
K0_3
F5A
LOGIC
MLOGIC
RIPPLE
RAM
ROM
PFU MODES
FSDMUX
0
K7_0MUX A K7
B
K7_2MUX C
D
K6_0MUX A K6
B
K6_2MUX C
D
AMUX
H7H6MUX
LUT6MUX
DIN7
0
DIN7MUX
DIN6
0
DIN6MUX
A K5
B
C
D
A K4
B
C
D
FSCMUX
0
H5H4MUX
SR1MODEATTR
SR1MODE
CE1_OVER_LSR1
LSR1_OVER_CE1
RSYNC1
CLK1
SEL1
CE1
LSR1
CIN
CLK0
SEL0
CE0
SR0MODEATTR
SR0MODE
CE0_OVER_LSR0
LSR0_OVER_CE0
ASYNC0
LSR0
DIN5
0
DIN5MUX
DIN4
0
CLK1MUX DIN4MUX
0
SEL1MUX
0
CE47MUX
CE1MUX 1
1
LSR1MUX 0 LSR47MUX
0
CINMUX
0
CLK0MUX
0
SEL0MUX
0
CEBMUX
1
CE0MUX
1
0 CE03MUX
LSRBMUX
1
LSR0MUX
0
0 LSR03MUX
FSBMUX
0
K3_0MUX
A
K3
B
K3_2MUX C
D
K2_0MUX A K2
B
K2_2MUX C
D
BMUX
H3H2MUX
LUT6MUX
DIN3
0
DIN3MUX
DIN2
0
DIN2MUX
GSR
ENABLED
DISABLED
A K1
B
C
D
A K0
B
C
D
F5AMUX
0
H1H0MUX
DIN1
0
DIN1MUX
DIN0
0
DIN0MUX
F7
REG7
D0
D1
SD
SP
CK
LSR
Q7
RESET
SET
DEL0
DEL1
DEL2
DEL3 F6
REG6
D0
D1
SD
SP
CK
LSR
Q6
RESET
SET
DEL0
DEL1
DEL2
DEL3
LUT647
F5
REG5
D0
D1
SD
SP
CK
LSR
Q5
RESET
SET
DEL0
DEL1
DEL2
DEL3 F4
REG4
D0
D1
SD
SP
CK
LSR
RESET
SET
REGMODE_TOP
Q4
DEL0
DEL1
DEL2
DEL3
FF
REG 4 THROUGH 7
LATCH
COUT
THIS IS ALWAYS A FLIPFLOP
REG8
D0
SP
CK
LSR
RECCOUT
RESET
SET
DEL0
DEL1
DEL2
DEL3
F3
REG3
D0
D1
SD
SP
CK
LSR
Q3
RESET
SET
DEL0
DEL1
DEL2
DEL3 F2
REG2
D0
D1
SD
SP
CK
LSR
Q2
RESET
SET
DEL0
DEL1
DEL2
DEL3
LUT603
F1
REG1
D0
D1
SD
SP
CK
LSR
Q1
RESET
SET
DEL0
DEL1
DEL2
DEL3 F0
REG0
D0
D1
SD
SP
CK
LSR
Q0
RESET
SET
DEL0
DEL1
DEL2
DEL3
REGMODE_BOT
FF
REG 0 THROUGH 3
LATCH
Note: All multiplexers without select inputs are configuration selector multiplexers.
5-9714(F)
Figure 3. Simplified PFU Diagram
10
Lucent Technologies Inc.
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