OR4E10 데이터 시트보기 (PDF) - Agere -> LSI Corporation

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OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

ORCA Series 4 FPGAs

Preliminary Data Sheet

December 2000

Table of Contents

Contents

Page Contents

Page

Programmable Features............................................. 1

System Features .........................................................4

Product Description .....................................................6

Architecture Overview .............................................6

Programmable Logic Cells ..........................................7

Programmable Function Unit ...................................8

Look-Up Table Operating Modes ..........................11

Supplemental Logic and Interconnect Cell ............21

PLC Latches/Flip-Flops .........................................25

Embedded Block RAM ..............................................27

EBR Features ........................................................27

Routing Resources ...................................................31

Clock Distribution Network ........................................31

Primary Clock Nets ................................................31

Secondary Clock and Control Nets .......................31

Edge Clock Nets ....................................................31

Programmable Input/Output Cells .............................31

Programmable I/O .................................................31

Inputs .....................................................................34

Special Function Blocks ............................................38

Microprocessor Interface (MPI) .................................48

Embedded System Bus (ESB) ..................................49

Phase-Locked Loops.................................................52

FPGA States of Operation.........................................55

Initialization ............................................................ 56

Configuration .........................................................56

Start-Up .................................................................56

Reconfiguration .....................................................60

Partial Reconfiguration ..........................................60

Other Configuration Options ..................................60

Bit Stream Error Checking .....................................62

FPGA Configuration Modes.......................................62

Master Parallel Mode.............................................63

Master Serial Mode ...............................................64

Asynchronous Peripheral Mode ............................65

Microprocessor Interface Mode .............................66

Slave Serial Mode .................................................70

Slave Parallel Mode...............................................70

Daisy Chaining ......................................................71

Daisy-Chaining with Boundary Scan .....................72

Absolute Maximum Ratings.......................................72

Recommended Operating Conditions .......................73

Electrical Characteristics ...........................................73

Pin Information ..........................................................75

Pin Descriptions.....................................................75

Package Compatibility ...........................................78

Package Thermal Characteristics Summary ...........118

ΘJA ......................................................................118

ψJC ......................................................................118

ΘJC ......................................................................118

ΘJB ......................................................................118

Package Thermal Characteristics............................119

Package Coplanarity ...............................................119

Package Parasitics ..................................................119

Package Outline Diagrams......................................120

Terms and Definitions..........................................120

Package Outline Drawings ......................................121

352-Pin PBGA .....................................................121

432-Pin EBGA .....................................................122

680-Pin PBGAM ..................................................123

Ordering Information................................................124

Figure

Page

Figure 1. Series 4 Top-Level Diagram ........................7

Figure 2. PFU Ports .....................................................9

Figure 3. Simplified PFU Diagram .............................10

Figure 4. Simplified F4 and F5 Logic Modes .............12

Figure 5. Simplified F6 Logic Modes .........................13

Figure 6. MUX 4 x 1...................................................13

Figure 7. MUX 8 x 1...................................................14

Figure 8. Softwired LUT Topology Examples.............15

Figure 9. Ripple Mode ...............................................16

Figure 10. Counter Submode ....................................17

Figure 11. Multiplier Submode...................................18

Figure 12. Memory Mode ..........................................19

Figure 13. Memory Mode Expansion

Example—128 x 8 RAM ........................................21

Figure 14. SLIC All Modes Diagram ..........................22

Figure 15. Buffer Mode ..............................................23

Figure 16. Buffer-Buffer-Decoder Mode ....................23

Figure 17. Buffer-Decoder-Buffer Mode ....................24

Figure 18. Buffer-Decoder-Decoder Mode ................24

Figure 19. Decoder Mode..........................................25

Figure 20. Latch/FF Set/Reset Configurations ..........26

Figure 21. EBR Read and Write Cycles

with Write Through ................................................29

Figure 22. Series 4 PIO Image from

ORCA Foundry ......................................................33

Figure 23. ORCA High-Speed I/O Banks ..................36

Figure 24. PIO Shift Register.....................................38

Figure 25. Printed-Circuit Board with Boundary-

Scan Circuitry ........................................................39

Figure 26. Boundary-Scan Interface..........................40

Figure 27. ORCA Series Boundary-Scan

Circuitry Functional Diagram .................................43

Figure 28. TAP Controller State Transition

Diagram .................................................................44

Figure 29. Boundary-Scan Cell .................................45

Figure 30. Instruction Register Scan Timing

Diagram .................................................................46

Figure 31. PLL_VF External Requirements...............53

Figure 32. PLL Naming Scheme ...............................54

2

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