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OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

Preliminary Data Sheet

December 2000

ORCA Series 4 FPGAs

Table of Contents (continued)

Contents

Page Contents

Page

Figure 33. FPGA States of Operation ....................... 55

Figure 34. Initialization/Configuration/Start-Up

Waveforms............................................................. 57

Figure 35. Start-Up Waveforms................................. 59

Figure 36. Serial Configuration Data

Format—Autoincrement Mode .............................. 60

Figure 37. Serial Configuration Data

Format—Explicit Mode .......................................... 60

Figure 38. Master Parallel

Configuration Schematic ....................................... 63

Figure 39. Master Serial Configuration Schematic.... 65

Figure 40. Asynchronous Peripheral Configuration... 66

Figure 41. PowerPC/MPI Configuration Schematic... 67

Figure 42. Configuration Through MPI ...................... 68

Figure 43. Readback Through MPI ........................... 69

Figure 44. Slave Serial Configuration Schematic ...... 70

Figure 45. Slave Parallel Configuration Schematic ... 71

Figure 46. Daisy-Chain Configuration Schematic ..... 72

Figure 47. Package Parasitics ................................. 120

Table

Page

Table 1. ORCA Series 4—Available FPGA Logic ....... 1

Table 2. System Performance .................................... 5

Table 3. Look-Up Table Operating Modes ................ 11

Table 4. Control Input Functionality .......................... 11

Table 5. Ripple Mode Equality Comparator

Functions and Outputs .......................................... 18

Table 6. SLIC Modes ................................................ 22

Table 7. Configuration RAM Controlled Latch/

Flip-Flop Operation................................................ 25

Table 8. ORCA Series 4— Available

Embedded Block RAM .......................................... 27

Table 9. RAM Signals ............................................... 28

Table 10. FIFO Signals ............................................ 29

Table 11. Constant Multiplier Signals ....................... 30

Table 12. 8 x 8 Multiplier Signals.............................. 30

Table 13. CAM Signals ............................................. 30

Table 14. Series 4 Programmable I/O Standards ..... 32

Table 15. PIO Options .............................................. 35

Table 16. PIO Register Control Signals .................... 35

Table 17. PIO Logic Options..................................... 36

Table 18. Compatible Mixed I/O Standards .............. 36

Table 19. LVDS I/O Specifications........................... 37

Table 20. LVDS Termination Pin ............................. 37

Table 21. Dedicated Temperature Sensing.............. 39

Table 22. Boundary-Scan Instructions ..................... 40

Table 23. Series 4E Boundary-Scan

Vendor-ID Codes................................................... 41

Table 24. TAP Controller Input/Outputs ................... 43

Table 25. Readback Options .................................... 46

Table 26. MPC 860 to ORCA MPI Interconnection .. 48

Table 27. Embedded System Bus/MPI Registers..... 50

Table 28. Interrupt Register Space Assignments ..... 50

Table 29. Status Register Space Assignments ........ 51

Table 30. Command Register Space Assignments .. 51

Table 31. PPLL Specifications.................................. 52

Table 32. DPLL DS-1/E-1 Specifications.................. 53

Table 33. Dedicated Pin Per Package ...................... 53

Table 34. STS-3/STM-1 DPLL Specifications........... 54

Table 35. Phase-Lock Loops Index .......................... 54

Table 36A. Configuration Frame Format

and Contents ......................................................... 61

Table 36B. Configuration Frame Format

and Contents for Embedded Block RAM............... 61

Table 37. Configuration Frame Size ......................... 62

Table 38. Configuration Modes................................. 63

Table 39. Absolute Maximum Ratings ...................... 73

Table 40. Recommended Operating Conditions....... 73

Table 41. Electrical Characteristics .......................... 73

Table 42. Pin Descriptions........................................ 75

Table 43. ORCA I/Os Summary ............................... 78

Table 44. 352-Pin PBGA Pinout ............................... 79

Table 45. 432-Pin EBGA .......................................... 89

Table 46. 680-Pin PBGAM Pinout ............................ 99

Table 47. ORCA Series 4 FPGAs Plastic

Package Thermal Guidelines .............................. 119

Table 48. ORCA Series 4 FPGAs

Package Parasitics .............................................. 119

Table 49. Series 4 Package Matrix

(Speed Grades)................................................... 124

Table 50. Package Options..................................... 124

Lucent Technologies Inc.

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