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OR4E10

ORCA® Series 4 Field-Programmable Gate Arrays

Agere -> LSI Corporation 

ORCA Series 4 FPGAs

Preliminary Data Sheet

December 2000

Programmable Features (continued)

— New register control in each PFU has two inde-

pendent programmable clocks, clock enables,

local set/reset, and data selects.

— New LUT structure allows flexible combinations of

LUT4, LUT5, new LUT6, 4-to-1 MUX, new

8-to-1 MUX, and ripple mode arithmetic functions

in the same PFU.

— 32 x 4 RAM per PFU, configurable as single- or

dual-port. Create large, fast RAM/ROM blocks

(128 x 8 in only eight PFUs) using the supplemen-

tal logic and interconnect cell (SLIC) decoders as

bank drivers.

— Softwired LUTs (SWL) allow fast cascading of up

to three levels of LUT logic in a single PFU

through fast internal routing which reduces routing

congestion and improves speed.

— Flexible fast access to PFU inputs from routing.

— Fast-carry logic and routing to all four adjacent

PFUs for nibble-, bytewide, or longer arithmetic

functions, with the option to register the PFU

carry-out.

s Abundant high-speed buffered and nonbuffered rout-

ing resources provide 2x average speed improve-

ments over previous architectures.

s Hierarchical routing optimized for both local and glo-

bal routing with dedicated routing resources. This

results in faster routing times with predictable and

efficient performance.

s SLIC provides eight 3-statable buffers, up to 10-bit

decoder, and PAL1-like and-or-invert (AOI) in each

programmable logic cell.

s New 200 MHz embedded quad-port RAM blocks, two

read ports, two write ports, and two sets of byte lane

enables. Each embedded RAM block can be config-

ured as:

— One 512 x 18 (quad-port, two read/two write) with

optional built-in arbitration.

— One 256 x 36 (dual-port, one read/one write).

— One 1K x 9 (dual-port, one read/one write).

— Two 512 x 9 (dual-port, one read/one write for

each).

— Two RAMs with arbitrary number of words whose

sum is 512 or less by 18 (dual-port, one read/one

write).

— Supports joining of RAM blocks.

— Two 16 x 8-bit content addressable memory

(CAM) support.

— FIFO 512 x 18, 256 x 36, 1K x 9 or dual 512 x 9.

— Constant multiply (8 x 16 or 16 x 8).

— Dual-variable multiply (8 x 8).

s Built-in testability.

— Full boundary-scan (IEEE 2 1149.1 and Draft

1149.2 joint test access group (JTAG)).

— Programming and readback through boundary-

scan port compliant to IEEE Draft 1532:D1.7.

— TS_ALL testability function to 3-state all I/O pins.

— New temperature-sensing diode used to deter-

mine device junction temperature.

System Features

s PCI local bus compliant.

s Improved PowerPC3860 and PowerPC II high-speed

(66 MHz) synchronous MPI interface can be used for

configuration, readback, device control, and device

status, as well as for a general-purpose interface to

the FPGA logic, RAMs, and embedded standard-cell

blocks. Glueless interface to synchronous PowerPC

processors with user-configurable address space

provided.

s New embedded AMBA4 specification 2.0 AHB sys-

tem bus (ARM 4processor) facilitates communication

among the microprocessor interface, configuration

logic, EBR, FPGA logic, and embedded standard-cell

blocks. Embedded 32-bit internal system bus plus

4-bit parity interconnects FPGA logic, microproces-

sor interface (MPI), embedded RAM blocks, and

embedded standard-cell blocks with 100 MHz bus

performance. Included are built-in system registers

that act as the control and status center for the

device.

s New network phase-locked loops (PLLs) meet ITU-T

G.811 specifications and provide clock conditioning

for DS-1/E-1 and STS-3/STM-1 applications.

s Flexible general-purpose programmable PLLs offer

clock multiply (up to 8x), divide (down to 1/8x), phase

shift, delay compensation, and duty cycle adjustment

combined. Improved built-in clock management with

programmable phase-locked loops (PPLLs) provide

optimum clock modification and conditioning for

phase, frequency, and duty cycle from 20 MHz up to

420 MHz. Each PPLL provides two separate clock

outputs.

1. PAL is a trademark of Advanced Micro Devices, Inc.

2. IEEE a is registered trademark of The Institute of Electrical and

Electronics Engineers, Inc.

3. PowerPC is a registered trademark of International Business

Machines, Corporation.

4. AMBA and ARM are trademarks of ARM Limited.

4

Lucent Technologies Inc.

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