MSM80C86A-10GS 데이터 시트보기 (PDF) - Oki Electric Industry

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MSM80C86A-10GS

16-Bit CMOS MICROPROCESSOR

Oki Electric Industry 

¡ Semiconductor

MSM80C86A-10RS/GS/JS

PIN DESCRIPTION

AD0 - AD15

ADDRESS DATA BUS: Input/Output

These lines are the multiplexed address and data bus.

These are the address bus at the T1 cycle and the data bus at the T2, T3, TW and T4 cycles.

At the T1 cycle, AD0 low indicates Data Bus Low (D0-D7) Enable. These lines are high

impedance during interrupt acknowledge and hold acknowledge.

A16/S3. A17/S4, A18/S5, A19/S6

ADDRESS/STATUS: Output

These are the four most significant addresses, at the T1 cycle. Accessing I/O port address,

these are low at T1 cycles. These lines are Status lines at T2, T3, TW and T4 cycles. S3 and S4

are encoded as shown.

S3

S4

0

0

1

0

0

1

1

1

Characteristics

Alternate Data

Stack

Code or None

Data

These lines are high impedance during hold acknowledge.

BHE/S7

BUS HIGH ENABLE/STATUS: Output

This line indicates Data Bus High Enable (BHE) at the T1 cycle. This line is status line at T2,

T3, TW and T4 cycles.

RD

READ: Output

This line indicates that CPU is in the memory or I/O read cycle.

This line is the read strobe signal when CPU read data from memory or I/O device. This line

is active low.

This line is high impedance during hold acknowledge.

READY

READY:Input

This line indicates to the CPU that the addressed memory or I/O device is ready to read or

write.

This line is active high. If the setup and hold time is out of specification, illegal operation will

occur.

INTR

INTERRUPT REQUEST: Input

This line is the level triggered interrupt request signal which is sampled during the last clock

cycle of instruction and string manipulation.

It can be internally masked by software.

This signal is active high and internally synchronized.

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