PI6C3Q993Q 데이터 시트보기 (PDF) - Pericom Semiconductor Corporation
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PI6C3Q993Q Datasheet PDF : 10 Pages
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PI6C3Q991, PI6CQ3993
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Logic Block Diagrams
PI6C3Q991
GND/sOE
PI6C3Q993
GND/sOE
VCCQ/PE
REF
PLL
FB
3
FS
Skew
1Q0
Select
33
1Q1
1F1:0
VCCQ/PE
Skew
2Q0
Select
33
2Q1
2F1:0
REF
PLL
Skew
Select
33
FB
3Q0
3
3Q1
3F1:0
FS
Skew
4Q0
Select
33
4Q1
4F1:0
Skew
1Q0
Select
33
1Q1
1F1:0
Skew
2Q0
Select
33
2Q1
2F1:0
Skew
3Q0
Select
33
3Q1
3F1:0
4Q0
4Q1
Pin Descriptions
Pin Name Type
Functional Description
REF
IN Reference Clock input
FB
IN Feedback Input
TEST(1)
IN
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew selections
(see table 3) remain in effect. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q0 and 3Q1) in a LOW state - 3Q0
GND/sOE(1)
IN
or 3Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and
GND/sOE is HIGH, the nF [1:0] pins act as output disable controls for individual banks when nF [1:0] = LL.
Set GND/sOE LOW for normal operation.
VCCQ/PE
IN
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the
negative/positive edge of the reference clock.
nF [1:0]
IN 3-level inputs for selecting 1 of 9 skew taps or frequency range.
FS
IN Selects appropriate oscillator circuit based on anticipated frequency range. See table 2
nQ [1:0]
OUT 4 output banks of 2 outputs, with programmable skew. On the PI6C3Q993 4Q1:0 are fixed zero skew outputs.
VCCN
PWR Power supply for output buffers
VCCQ
PWR Power supply for phase locked loop and other internal circuitry
GND
PWR Ground
Note:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[1:0] =LL functioning as an output disable control for
individual output banks. Skew selections (see Table 3) remain in effect unless nF[1:0] = LL.
2
PS8449A 10/09/00
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