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PI6C3Q993Q 데이터 시트보기 (PDF) - Pericom Semiconductor Corporation

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PI6C3Q993Q
PERICOM
Pericom Semiconductor Corporation PERICOM
PI6C3Q993Q Datasheet PDF : 10 Pages
1 2 3 4 5 6 7 8 9 10
PI6C3Q991, PI6C3Q993
112233445566778899001122334455667788990011223344556677889900112211223344556677889900112233445566778899001122334455667788990011221132233.34455V667788P9900r11o22g3344r55a6677m8899m001122a3344b55l66e7788S9900k11e2211w223344P5566L7788L9900C1122l33o4455c66k778899D0011r22i33v4455e66r7788S9900u11p2211e22r33C4455l66o7788c99k0011®22
Table 9. Switching Characteristics Over Operating Range
Symbol
Description
FNOM
tRPWH
tRPWL
VCO frequency range
REF pulse width HIGH(11)
REF pulse width LOW(11)
tU
tSKEWPR
tSKEW0
tSKEW1
tSKEW2
tSKEW3
tSKEW4
tDEV
tPD
tODCV
tPWH
tPWL
tORISE
tOFALL
tLOCK
Programmable skew time unit
Zero output matched-pair skew (xQ0, xQ1)(1,2,3)
Zero output skew (all outputs) CL = 0pF(1,4)
Output skew (rise-rise, fall-fall, same class outputs) (1,5)
Output skew (rise-fall, nominal-inverted, divided-divided) (1,5)
Output skew (rise-rise, fall-fall, different class outputs) (1,5)
Output skew (rise-fall, nominal-divided, divided-inverted) (1,5)
Device-to-device skew (1,2,6)
REF input to FB propagation delay (1,8)
Output duty cycle varation from 50%(1)
Output HIGH time deviation from 50%(1,9)
Output LOW time deviation from 50%(1,10)
Output rise time (1)
Output fall time (1)
PLL lock time (1,7)
tJR
Cycle-to-cycle output jitter(1) RMS
Peak-to-peak
PI6C3Q991-2
PI6C3Q993-2
Min. Typ. Max.
PI6C3Q991-5
PI6C3Q993-5
Min. Typ. Max.
PI6C3Q991
PI6C3Q993
Min. Typ. Max.
Units
see Table 2
see Table 2
see Table 2
3.0
3.0
3.0
ns
3.0
3.0
3.0
see Table 3
see Table 3
see Table 3
0.05 0.20
0.1 0.25
0.1 0.25
0.1 0.25
0.25 0.5
0.3 0.75
0.25 0.50
0.6 0.7
0.6 1.0
0.30 1.2
0.5 1.2
1.0 1.5
0.25 0.50
0.5 0.7
0.7 1.2
0.50 0.90
0.5 1.0
1.2 1.7
0.75
1.25
1.65 ns
–0.25 0 0.25 –0.5 0 0.5 –0.7 0 0.7
–1.2 0 1.2 –1.2 0 1.2 –1.2 0 1.2
2.0
2.5
3.0
2.5
3.0
3.5
0.15 1.0 1.8 0.15 1.0 1.8 0.15 1.5 2.5
0.15 1.0 1.8 0.15 1.0 1.8 0.15 1.5 2.5
0.5
0.5
0.5 ms
25
40
40
ps
200
200
200
Notes:
1. All timing tolerances apply for F NOM 25MHz. Guaranteed by design and characterization, not subject to 100%
production testing.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t U delay
has been selected when all are loaded with the specified load.
3. tSKEWPR is the skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
4. tSKEW0 is the skew between outputs when they are selected for 0tU.
5. There are 3 classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH),
and Divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode).
6. t DEV is the output-to-output skew between any two devices operating under the same conditions (VCC , ambient
temperature, air flow, etc.)
7. tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is
stable and within normal operating limits. This parameter is measured from the application of a new signal or
frequency at REF or FB until tPD is within specified limits.
8. tPD is measured with REF input rise and fall times (from 0.8V to 2.0V) of 1.0ns.
9. Measured at 2.0V.
10. Measured at 0.8V.
11. Refer to Table12 for more detail.
7
PS8449A 10/09/00

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