PI6C3Q993Q 데이터 시트보기 (PDF) - Pericom Semiconductor Corporation
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PI6C3Q993Q Datasheet PDF : 10 Pages
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PI6C3Q991, PI6CQ3993
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Table 12. Input Timing Requirements
Symbol
Description
Min. Max. Units
tR, tF Maximum input rise and fall times, 0.8V to 2.0V
10 ns/V
tPWC Input clock pulse, HIGH or LOW
3
ns
DH Input duty cycle
10
90
%
Notes:
1. Input timing requirements are guaranteed by design but not tested. Where pulse width implied by DH is
less than tPWC limit, tPWC limit applies.
REF
tPD
FB
Q
Other Q
Inverted Q
REF Divided by 2
REF Divided by 4
tREF
tRPWH
tRPWL
tODCV tODCV
ttSSKKEEWW0P, R1
tSKEW3,4
tSKEW1,3,4
ttSSKKEEWW0P, R1
tSKEW2
tSKEW3,4
tJR
tSKEW2
tSKEW3,4
tSKEW2,4
AC Timing Diagram
Notes:
VCCQ/PE: The AC timing diagram above applies to VCCQ/PE=VCC. For VCCQ/PE=GND, the negative edge of FB aligns with the negative edge of REF,
divided outputs change on the negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.
Skew: The time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are
loaded with 20pF and terminated with 75Ohm to VCC/2.
tSKEWPR: The skew between a pair of outputs (xQ0 and xQ1) when all eight outputs are selected for 0tU.
tSKEW0: The skew between outputs when they are selected for 0t U.
tDEV:
The output-to-output skew between any two devices operating under the same conditions (VCC, ambient temperature, air flow, etc.)
tODCV: The deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications.
tLOCK: The time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating
limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits.
tPWH is measured at 2.0V.
tPWL is measured at 0.8V.
tORISE and tOFALL are measured between 0.8V and 2.0V.
8
PS8449A 10/09/00
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