M80C186EB-13 데이터 시트보기 (PDF) - Intel

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M80C186EB-13

16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR

Intel 

M80C186EB

Any carry out from the 16-bit addition is ignored

8-bit displacements are sign extended to 16-bit val-

ues

Combinations of these three address elements de-

fine the six memory addressing modes described

below

 Direct Mode The operand’s offset is contained in

the instruction as an 8- or 16-bit displacement el-

ement

 Register Indirect Mode The operand’s offset is in

one of the registers SI DI BX or BP

 Based Mode The operand’s offset is the sum of

an 8- or 16-bit displacement and the contents of

a base register (BX or BP)

 Indexed Mode The operand’s offset is the sum

of an 8- or 16-bit displacement and the contents

of an index register (SI or DI)

 Based Indexed Mode The operand’s offset is the

sum of the contents of a base register and an

index register

 Based Indexed Mode with Displacement The op-

erand’s offset is the sum of a base register’s con-

tents an index register’s contents and an 8- or

16-bit displacement

DATA TYPES

The M80C186EB directly supports the following data

types

 Integer A signed binary numeric value contained

in an 8-bit byte or 16-bit word All operations as-

sume a 2’s complement representation Signed

32- and 64-bit integers are supported using the

M80C187 Numerics Coprocessor

 Ordinal An unsigned binary numeric value con-

tained in an 8-bit byte or 16-bit word

 Pointer A 16- or 32-bit quantity composed of a

16-bit offset component or a 16-bit segment

base component and a 16-bit offset component

 String A contiguous sequence of bytes or words

A string may contain from 1 Kbyte to 64 Kbytes

 ASCII A byte representation of alphanumeric and

control characters using the ASCII standard of

character representation

 BCD A byte (unpacked) representation of the

decimal digits 0– 9

 Packed BCD A byte (packed) representation of

two decimal digits (0 – 9) One digit is stored in

each nibble (4 bits) of the byte

 Floating Point A signed 32- 64- or 80-bit real

number representation Floating point operands

are supported when using the M80C187 Numeric

Coprocessor

In general individual data elements must fit within

defined segment limits

INTERRUPTS

An interrupt transfers execution to a new program

location The old program address (CS IP) and ma-

chine state (F) are saved on the stack to allow re-

sumption of the interrupted program Interrupts fall

into three classes hardware initiated software (pro-

gram) initiated and instruction exception initiated

Hardware initiated interrupts occur in response to an

external or internal input and are classified as non-

maskable or maskable

Programs may cause an interrupt by executing the

‘‘INT’’ instruction Instruction exceptions occur when

an illegal opcode has been fetched into the queue

and is read by the execution unit Another type of

exception can be generated when executing an

‘‘ESC’’ instruction

For all cases except the ‘‘ESC’’ exception the return

address from an exception will point at the instruc-

tion immediately following the instruction causing

the exception The return address after an ‘‘ESC’’

exception will point back to the ESC instruction

causing the exception or to the segment override

prefix immediately preceding the ESC instruction if

the prefix was present

A table containing up to 256 pointers defines the

proper interrupt service routine for each interrupt In-

terrupts 0 – 31 are reserved by Intel Table 2 shows

the M80C186EB predefined type and default priority

levels For each interrupt an 8-bit vector (Vector

Type) identifies the appropriate table entry Multiply-

ing the 8-bit vector by 4 defines the vector address

INT instructions contain or imply the vector type and

allow access to all 256 interrupts

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