VQ87C196KC 데이터 시트보기 (PDF) - Intel
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VQ87C196KC Datasheet PDF : 23 Pages
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M87C196KC M87C196KD
AC Characteristics (Continued)
For user over specified operating conditions
The M87C196KC KD will meet these specifications
Symbol
Description
Min
Max
FXTAL
Frequency on XTAL1
35
16
35
20
TOSC
1 FXTAL
62 5
286
50
286
TXHCH
TCLCL
TCHCL
TCLLH
TLLCH
TLHLH
TLHLL
TAVLL
TLLAX
TLLRL
TRLCL
TRLRH
TRHLH
TRLAZ
XTAL1 High to CLKOUT High or Low
CLKOUT Cycle Time
CLKOUT High Period
CLKOUT Falling Edge to ALE Rising
ALE Falling Edge to CLKOUT Rising
ALE Cycle Time
ALE High Period
Address Setup to ALE Falling Edge
Address Hold after ALE Falling Edge
ALE Falling Edge to RD Falling Edge
RD Low to CLKOUT Falling Edge
RD Low Period
RD Rising Edge to ALE Rising Edge
RD Low to Address Float
10
110
2 TOSC
TOSC b 10 TOSCa20
b5
15
b29
a15
4 TOSC
TOSC b 10 TOSCa15
TOSC b 15
TOSC b 49
TOSC b 36
0
30
TOSC b 5
TOSC
TOSC a 25
15
30
TLLWL
TCLWL
TQVWH
TCHWH
TWLWH
TWHQX
TWHLH
TWHBX
TWHAX
TRHBX
TRHAX
ALE Falling Edge to WR Falling Edge
CLKOUT Low to WR Falling Edge
Data Stable to WR Rising Edge
CLKOUT High to WR Rising Edge
WR Low Period
Data Hold after WR Rising Edge
WR Rising Edge to ALE Rising Edge
BHE INST after WR Rising Edge
AD8–15 HOLD after WR Rising
BHE INST after RD Rising Edge
AD8–15 HOLD after RD Rising
TOSC b 10
0
TOSC b 23
b10
TOSC b 30
TOSC b 30
TOSC b 10
TOSC b 10
TOSC b 50
TOSC b 10
TOSC b 25
25
15
TOSC a 15
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
NOTES
1 Assuming back-to-back bus cycles
2 8-Bit bus only
3 If wait states are used add 2 TOSC N where N e number of wait states
4 Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns FOSC e 16 MHz
Notes
KC KD-16
KD-20
KC KD-16
KD-20
(Note 3)
(Note 3)
(Note 1)
KC-16
KD-16 20
(Note 3)
(Note 1)
(Note 2)
(Note 2)
10
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