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SAA3500H

Digital audio broadcast channel decoder

Philips Electronics 

Philips Semiconductors

Digital audio broadcast channel decoder

Preliminary specification

SAA3500H

In the CIR output mode the channel impulse response is clocked out in a burst of N (unsigned) samples at 64 kHz each

frame after CIR processing (bit SyncBusy = logic 0). The edges of the frame trigger signal (OIQ) allow to trigger a CIR

display either at the start of the symbol or at the start of the symbol guard. In the latter case the CIR peak for a Gaussian

channel will be at the left of the display.

9.4 Serial output interface

The serial output interface is intended for transferring up to three sub-channels to the source decoder(s) with a total

maximum bit rate of 384 kbit/s. The sub-channels for these outputs should be selected with the appropriate I2C or L3

commands. The output clock is 384 kHz. Each sub-channel has its own serial data and data valid line, but the clock is

common. Serial output data shall be latched on the rising edge of SOC.

SOC

SOD

SOV

Fig.8 DAB3 serial output.

9.5 Simple full capacity output

This interface provides serial access to all the Viterbi decoder output bits without any formatting. Transmission framing

is indicated by the CFIC window, which can also be used to separate the FIC data (CFIC = HIGH) from the Main Service

Channel (MSC) data (CFIC = LOW). The bit CFICMode can be used to signal on CFIC the beginning of the selected

sub-channels (CFICMode = logic 0). The clock is a 3072 kHz burst clock, activated for each new output bit.

Accompanied with the data is the error flag, obtained by re-encoding the Viterbi output bits and comparison with the

corresponding Viterbi decoder input bits (REF = HIGH for error bit).

CFIC

RDC

SFCO

REF

CFICMode = 0

Fig.9 Simple full capacity output (CFICMode = logic 1).

9.6 RDI output

For external use a bi-phase modulated output (RDO) is provided, which carries all the FIC and MSC data, formatted

according to the DAB receiver data interface specification “EN 50255”, which is based on the IEC 60958 digital audio

interface. Optionally, a clock (6144 kHz) and word select signal (48 kHz) can be provided (instead of SFCO signals).

Transmitter Identification Information (TII) is not signalled on this RDI. The FIC however is always signalled, with the

Cyclic Redundancy Check (CRC) performed and the Error Check Field containing the resulting CRC (normally 0).

Selected sub-channels will be directed to the RDI interface in the extended capacity mode (22 bits for MSC), but the

number of RDI frames and the reliability are not signalled (i.e., set to all logic 0s and all logic 1s, respectively).

2000 Jun 14

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