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SAA3500H

Digital audio broadcast channel decoder

Philips Electronics 

Philips Semiconductors

Digital audio broadcast channel decoder

Preliminary specification

SAA3500H

9 INTERFACE DESCRIPTION

9.1 Input interface

The input interface can be used in 3 different modes, depending on the bypass (BYP) and IQ Select (IQS) pins. Digital

input data should be in two’s complement format (optionally: offset binary) and synchronized with the ADCLK output

signal. Input data are read on the rising edge of ADCLK.

Table 1 Input modes

BYP

0

1

1

IQS

DESCRIPTION

clk digital baseband input sampled at 2048 kHz and with I and Q data multiplexed

0 digital IF input sampled at 8192 kHz, internal I/Q demodulator

1 digital IF input sampled at 8192 kHz, internal I/Q demodulator with I and Q swapped

In case of baseband input the IQ select signal shall indicate whether the current sample is either I or Q data (INP[9:0]).

ADCLK

INP[9:0]

IQS

4096 kHz

Q0

I1

Q1

I2

Q2

10 bits

2048 kHz

Fig.3 Baseband input signals (BYP = LOW).

Digital IF input is, typically, at a frequency of 2048 kHz. It is possible to apply sub-sampling on a N × 8.192 ±2.048 MHz

(N = 1, 2, 3,...,19) IF signal, but care should be taken with the jitter of the crystal clock, which is proportional to N.

ADCLK

INP[9:0]

8192 kHz

10 bits

Fig.4 IF input signals [BYP = HIGH, IQS = LOW (no swap) or HIGH (swap)].

To use the on-chip null detector, pins FSI and FSO shall simply be connected to each other.

When using an external null detector, the FSI input shall indicate the position of the null symbol in the baseband signal

(FSI = LOW). The negative edge may have a maximum delay of 512 samples with respect to an ideal null detector. The

delay compensation can be set via the I2C/L3 interface (register ATCWinControl). The FSI input provides edge jitter

suppression of up to 40 samples starting from the first negative edge. Once the SAA3500H is in symbol processing

mode, the FSI signal is ignored. During the null detection state, the Sync Lock Indicator (SLI) will be continuously LOW.

9.2 Memory interface

An external SRAM memory of either 128 or 256 kbytes is required to store the metrics from the data de-interleaver for

half (432 CUs) or full (864 CUs) decoding capacity, respectively. The upper address line A17 is available both true and

inverted (A17) to allow memory extension without an address decoder. 3.3 V RAMs should be used with either an 8 or

(2 ×) 4-bit data bus and an access time of ≤80 ns. Input data are read on the rising edge of RD, output data shall be

latched on the rising edge of WR.

2000 Jun 14

9

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