SC18IS600 데이터 시트보기 (PDF) - NXP Semiconductors.

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SC18IS600

SPI to I2C-bus interface

NXP Semiconductors. 

NXP Semiconductors

5. Pinning information

5.1 Pinning

SC18IS600

SPI to I2C-bus interface

GPIO0 1

CS 2

RESET 3

VSS 4

MISO 5

MOSI 6

SDA 7

SCL 8

SC18IS600IPW

SC18IS600IPW/S8

16 IO5

15 WAKEUP/IO4

14 INT

13 GPIO3

12 VDD

11 SCLK

10 GPIO2

9 GPIO1

002aab713

Fig 2. SC18IS600 pin configuration for TSSOP16

terminal 1

index area

CS 1

RESET 2

VSS 3

MISO 4

MOSI 5

SDA 6

SC18IS600IBS

18 WAKEUP/IO4

17 INT

16 GPIO3

15 VDD

14 SCLK

13 GPIO2

Transparent top view

002aad707

Fig 3. SC18IS600 pin configuration for HVQFN24

5.2 Pin description

Table 3.

Symbol

GPIO0

CS

RESET

VSS

MISO

MOSI

SDA

SCL

GPIO1

GPIO2

SCLK

VDD

GPIO3

CLKIN

INT

Pin description

Pin

TSSOP16 HVQFN24

1

23

2

1

3

2

4

3[1]

5

4

6

5

7

6

8

8

9

11

10

13

11

14

12

15

13

16

-

-

14

17

Type Description

I/O programmable I/O pin

I

Chip select. When CS is LOW, the SC18IS600 is selected.

I

Master Reset. When active (LOW), RESET sets internal registers to the

default values, and resets the I2C-bus and SPI hardware. See Table 4.

I

ground supply voltage

O SPI slave data output

I

SPI slave data input

I/O I2C-bus serial data input/output

O

I2C-bus serial clock output

I/O programmable I/O pin

I/O programmable I/O pin

I

SPI clock input

I

2.4 V to 3.6 V supply voltage

I/O programmable I/O pin

I

external clock input

O Interrupt. When active (LOW), INT informs the CPU that the SC18IS600

has an interrupt to be serviced.

INT is reset (deactivated) either when the I2CStat register is read or as a

result of a master reset (RESET). This pin is an open-drain pin.

SC18IS600

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 7.1 — 20 November 2017

© NXP Semiconductors N.V. 2017. All rights reserved.

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