SC18IS600 데이터 시트보기 (PDF) - NXP Semiconductors.
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SC18IS600 Datasheet PDF : 30 Pages
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NXP Semiconductors
SC18IS600
SPI to I2C-bus interface
6.2.1.4 Push-pull output configuration
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous strong
pull-up when the pin latch contains a logic 1. The push-pull mode may be used when
more source current is needed from a pin output.
The push-pull pin configuration is shown in Figure 7.
A push-pull pin has a Schmitt-triggered input that also has a glitch suppression circuit.
VDD
P
strong
pin latch data
input data
Fig 7. Push-pull output configuration
N
VSS
GPIO pin
glitch rejection
002aab885
6.2.2 I/O pins state register (IOState)
When read, this register returns the actual state of all programmable and
quasi-bidirectional I/O pins. When written, each register bit will be transferred to the
corresponding I/O pin programmed as output.
Table 6.
Bit
7:6
5
4
3
2
1
0
IOState - I/O pins state register (address 0x01) bit description
Symbol
Description
-
reserved
IO5
Set the logic level on the output pins.
IO4
GPIO3 (SC18IS600 only)
GPIO2
GPIO1
Write to this register:
logic 0 = set output pin to zero
logic 1 = set output pin to one
A read from this register returns states of all pins.
GPIO0
6.2.3 I2C-bus address register (I2CAdr)
The contents of the register represents the device’s own I2C-bus address. The most
significant bit corresponds to the first bit received from the I2C-bus after a START
condition. The least significant bit is not used, but should be programmed with a ‘0’.
I2CAdr is not needed for device operation, but should be configured so that its address
does not conflict with an I2C-bus device address used by the bus master.
SC18IS600
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 7.1 — 20 November 2017
© NXP Semiconductors N.V. 2017. All rights reserved.
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