STLC60243 데이터 시트보기 (PDF) - STMicroelectronics
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STLC60243 Datasheet PDF : 8 Pages
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STLC61256
12 CHANNEL DMT ADSL DATA PUMP
WITH EMBEDDED IP/ATM CELL PROCESSOR
DATA BRIEF
6 MAIN FEATURES
Figure 1. Package
■ Support for 12 independent ports.
■ Low power consumption
■ Category II Functionality: Trellis coding and
Echo cancellation
■ Flexible bin assignment: Supports ADSL over
POTS, ADSL over ISDN, all digital loop and
overlapping spectra.
■ TC layer supporting: STM TC, ATM TC and
PTM TC (as required by G.dmt.bis annex K)
■ Includes PerFlow Cell Processor
– AAL5/2 SAR
– Policing and Scheduling 4 priorities
– Supports ATM and IP simultaneously per port
– Full switching capability
■ No external memory needed for Interleave
memory nor modem SW (for advanced PerFlow
applications external SDRAM needed)
■ No real time requirements from the controller
■ Each modem can be different phase (startup/
Showtime) independently of other modems
■ Package: PBGA676 27x27mm
■ 0.13um CMOS technology
■ 1.2V core logic supply (3.3V for I/O)
■ -40ºC to +85ºC operation
7 DESCRIPTION
The STLC61256 twelve channels ADSL Transceiver
is an advanced component for ADSL Central Office
modem implementation. The embedded IP/ATM Cell
Processor allows to simplify the design of high densi-
ty CO line cards and to develop a single platform that
supports IP or ATM based equipments. It allows also
different line card architecture with the possibility to
have also chaining of several STLC61256 devices on
PBGA676 (27 x 27mm)
Table 1. Order Codes
Part Number
STLC61256
Package
PBGA676
the same card.
External DRAM is required only for full PerFlow fea-
ture support (layer 2 addressing like MAC or VPI/VCI
level, Hash support, high number of voice+data con-
nections per channel). The highly integrated device
supports category II ADSL functionalities, including
trellis coding and echo cancellation. The device em-
bodies 6 independent dual transceivers optimized for
Central Office operation, with bit rates of up to 3.0
Mbps upstream and 24 Mbps downstream. This de-
vice is ideal for power and area sensitive Central Of-
fice equipment, providing highest performance and
density while meeting all telecom grade equipment
requirements.
The STLC61256 is designed for minimal host control-
ler intervention during runtime operation. Combining
this feature with additional management interfaces
such as the serial host interface and the In-band Uto-
pia management interface provides many alterna-
tives for designs that significantly reduce operation
complexity and cost. Cost saving can be achieved by
using a singe low-cost controller to support high-den-
sity line-cards, saving the need for on-board flash
memory or even the entire host processor environ-
ment. The STLC61256 host interface provides a full
sup-port of the ADSL MIB, and a rich set of statistic
information and programmable fault alarms.
June 2004
4/8
This is preliminary information on a new product foreseen to be developed. Details are subject to change without notice.
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