SY100EP195V 데이터 시트보기 (PDF) - Micrel
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SY100EP195V Datasheet PDF : 18 Pages
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Micrel, Inc.
ECL Pro®
SY100EP195V
AC ELECTRICAL CHARACTERISTICS
VCC = 3.0 to 5.5V, VEE = 0V or VCC = 0V, VEE = –3.0 to –5.5V; TA = –40°C to +85°C.(12, 13)
TA = –40°C
TA = +25°C
Symbol
Parameter
Min Typ Max Min Typ Max
fMAX
tPD
Maximum Frequency(14)
Propagation Delay
IN to Q; D[0-10]=0
IN to Q; D[0-10]=1023
/EN to Q: D[0-10]=0
D10 to CASCADE
1650
9500
1600
300
2.5
2000
11500
2150
420
2450
13500
2600
500
1800
9800
1800
325
2.5
2050
12200
2300
450
2600
14000
2800
550
tRANGE
∆t
Lin
tSKEW
tS
Programmable Range
tPD(max)-tPD(min)
Step Delay(15)
D0 High
D1 High
D2 High
D3 High
D4 High
D5 High
D6 High
D7 High
D8 High
D9 High
Linearity(16)
Duty Cycle Skew(17)
tPHL-tPLH
Setup Time
D to LEN
D to IN(18)
/EN to IN(19)
7850
200
300
300
9450
9
25
42
75
142
296
532
1080
2100
4250
±10
0
140
150
8200 10000
10
26
42
80
143
300
540
1095
2150
4300
±10
25
200
0
300 160
300 170
tH
Hold Time
LEN to D 200
60
IN to /EN(20) 400 250
200 100
400 280
tR
Release Time
/EN to IN(21)
500
SETMAX to LEN 400 200
400 250
SETMIN to LEN 350 275
350 200
tJIT
Cycle-to-Cycle Jitter(22)
0.2
<1
0.2
<1
VPP
Input Voltage Swing (Differential) 150 800 1200 150 800 1200
tr
Output Rise/Fall Time
tf
20% to 80% (Q)
20% to 80% (CASCADE)
180 250
180 250
210 300
210 300
TA = +85°C
Min Typ Max
2.5
Unit
GHz
1950 2250 2750 ps
10600 13300 15800 ps
2000 2500 3000 ps
325 525 625 ps
8850 10950
ps
10
27
43
81
150
310
565
1140
2250
4500
±10
200
0
300 180
300 180
200
80
400 300
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
%LSB
ps
ps
ps
ps
ps
ps
ps
400 300
ps
350 335
ps
0.2
< 1 psRMS
150 800 1200 mV
230 325 ps
230 325 ps
Notes:
12. AC characteristics are guaranteed by design and characterization.
13. Measured using 750mV source, 50% duty cycle clock source, RL = 50Ω to VCC – 2V.
14. Refer to “Typical Operating Characteristics” for output swing performance.
15. The delays of the individual bits are cumulative.
16. Linearity is the deviation from the ideal delay.
17. Duty cycle skew guaranteed only for differential operation measured from the crosspoint of the input edge to the crosspoint of the corresponding
output edge.
18. Setup time defines the amount of time prior to an edge on IN, /IN that the D[0:9] bits must be set to guarantee the new delay will occur for that edge.
19. Setup time is the minimum that /EN must be asserted prior to the next transition of IN, /IN to prevent an output response greater than ±75mV to that
IN, /IN transition.
20. Hold time is the minimum time that /EN must remain asserted after a negative going IN or a positive going /IN to prevent an output response greater
than ±75mV to that IN, /IN transition.
21. Release time is the minimum time that /EN must be deasserted prior to the next IN, /IN transition to ensure an output response that meets the
specified IN to Q propagation delay and transition times.
22. This is the amount of generated jitter added to an otherwise jitter free clock signal, going from IN, /IN to Q, /Q, where the clock may be any frequency
between 0.0 and 2.5GHz.
M9999-120505
hbwhelp@micrel.com or (408) 955-1690
7
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