NT7701H-TABF3 데이터 시트보기 (PDF) - Novatek Microelectronics

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NT7701H-TABF3

160 Output LCD Segment/Common Driver

Novatek Microelectronics 

NT7701

Functional Description

1. Block description

1.1. Active Control

In the case of segment mode, controls the selection or

deselection of the chip. Following a LP signal input, and after

the select signal is input, a select signal is generated

internally until 160 bits of data have been read in. Once data

input has been completed, a select signal for cascade

connection is output, and the ship is deselected.

In the case of common mode, controls the input/output data

of bidirectional pins.

1.2. SP Conversion & Data Control

In the case of segment mode, keep input data which are 2

clocks of XCK at 4-bit parallel mode into latch circuit, or keep

input data which are 1 clock of XCK at 8-bit parallel mode

into latch circuit, after that they are put on the internal data

bus 8 bits at a time.

1.3. Data Latch Control

In the case of the segment mode, it selects the state of the

data latch, which reads in the data bus signals. The shift

direction is controlled by the control logic and for every 16

bits of data read in, the selection signal shifts one bit, based

on the state of the control circuit.

1.4. Data Latch

In the case of the segment mode, it latches the data on the

data bus. The latched state of each LCD driver output pin is

controlled by the control logic and the data latch control 160

bits of data are read in 20 sets of 8 bits.

1.5. Line Latch / Shift Register

In the case of the segment mode, all 160 bits which have

been read into the data latch, are simultaneously latched on

to the falling edge of the LP signal, and output to the level

shift block.

In the case of the common mode, shifts data from the data

input pin on to the falling edge of the LP signal.

1.6. Level Shifter

The logic voltage signal is level-shifted to the LCD driver

voltage level, and output to the driver block.

1.7. 4-Level Driver

It drives the LCD driver output pins from the line latch/shift

register data, selecting one of 4 levels (V0, V12, V43, VSS)

based on the S/C, FR and DISPOFF signals.

1.8. Control Logic

It controls the operation of each block. In the case of the

segment mode, when an LP signal has been input, all blocks

are reset and the control logic waits for the selection signal

output from the active control block. Once the selection

signal has been output, operation of the data latch and data

transmission are controlled, 160 bits of data are read in, and

the chip is deselected.

In the case of the common mode, it controls the direction of

the data shift.

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