JTS83102G0-1V1B 데이터 시트보기 (PDF) - Atmel Corporation
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JTS83102G0-1V1B Datasheet PDF : 56 Pages
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Transient and Switching Performances
Parameter
Test
Level Symbol
Min
Typ
Max
Unit
Transient Performance
Bit error rate (1)
4
BER
10-12
Error/
sample
ADC setting time (VIN - VINB = 400 mVpp)
Overvoltage recovery time
4
TS
4
ORT
1
ns
500
ps
ADC step response rise/fall time (10 - 90%)
80
100
ps
Overshoot
4
%
Ringback
2
%
Switching Performance and Characteristics
Maximum clock frequency (2)
Minimum clock frequency (2)
Minimum clock pulse width (high)
FSMax
2
2.2
Gsps
4
FSMin
150
200
Msps
4
TC1
0.2
0.25
2.5
ns
Minimum clock pulse width (low)
4
TC2
0.2
Aperture delay (2)
4
TA
Aperture uncertainty (2)
4
Jitter
Output rise/fall time for DATA (20 - 80%) (3)
4
TR/TF
Output rise/fall time for DATA READY (20 - 80%) (3)
4
TR/TF
Data output delay (4)
4
TOD
0.25
160
150
150
150
360
2.5
ns
ps
200
fs rms
200
ps
200
ps
ps
4
TDR
410
ps
Data ready output delay (4)
Output data to data ready propagation delay (5)
Data ready to output data propagation delay (5)
ITOD
4
minus
0
TDRI
50
100
ps
4
TD1
250
300
350
ps
4
TD2
150
200
250
ps
Output data pipeline delay
4
TPD
Clock
4.0
cycles
Data ready reset delay
4
TRDR
1000
ps
Notes:
1. Output error amplitude < ±6 LSB, Fs = 2 Gsps, TJ = 110°C
2. See “Definition of Terms” on page 35.
3. 50Ω // CLOAD = 2 pF termination (for each single-ended output). Termination load parasitic capacitance derating value:
50 ps/pF (ECL). See “Timing Information” on page 37.
4. TOD and TDR propagation times are defined at package input/outputs. They are given for reference only. See “Propagation
Time Considerations” on page 37.
5. Values for TD1 and TD2 are given for a 2 Gsps external clock frequency (50% duty cycle). For different sampling rates, apply
the following formula: TD1 = T/2 + (|TOD - TDR|) and TD2 = T/2 + (|TOD - TDR|), where T = clock period. This places the ris-
ing edge (True/False) of the differential data ready signal in the middle of the output data valid window. This gives maximum
setup and hold times for external data acquisition.
10 TS83102G0B
2101D–BDC–06/04
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