JTS83102G0-1V1B 데이터 시트보기 (PDF) - Atmel Corporation
부품명
상세내역
제조사
JTS83102G0-1V1B Datasheet PDF : 56 Pages
| |||
TS83102G0B
Electrical Operating Characteristics (Continued)
VCC = 5V ; VPLUSD = 0V (unless otherwise specified). ADC performances are independent of VPLUSD common mode
voltage and performances are guaranteed within the limits of the specified VPLUSD range (from -0.9V to 1.7V);
VEE = DVEE = -5V; VIN - VINB = 500 mVpp (full-scale single-ended or differential input);
clock inputs differential driven; analog-input single-ended driven.
Parameter
Test
Level Symbol
Min
Typ
Max
Unit
Analog input power level (50 Ω single-ended)
Analog input capacitance (die)
Input leakage current
Input resistance
- single-ended
- differential
Clock Inputs
4
PIN
4
CIN
4
IIN
4
RIN
49
4
RIN
98
-2
dBm
0.3
pF
10
µA
50
51
Ω
100
102
Ω
Logic common mode compatibility for clock inputs
Differential ECL to LVDS
Clock inputs common voltage range (VCLK or VCLKB)
(DC coupled clock input)
AC coupled for LVDS compatibility (common mode
4
VCM
-1.2
0
0.3
V
1.2V)
Clock input power level (low-phase noise sinewave
input)
4
50 Ω single-ended or 100 Ω differential
Clock input swing (single ended; with CLKB = 50 Ω
to GND)
4
PCLK
VCLK
-4
±200
0
±320
4
±500
dBm
mV
Clock input swing (differential voltage) - on each
clock input
4
VCLK
VCLKB
±141
±226
±354
mV
Clock input capacitance (die)
4
CCLK
0.3
pF
Clock input resistance
- single-ended
- differential ended
RCLK
45
RCLK
90
50
55
Ω
100
110
Ω
Digital Inputs (SDAEN, PGEB, DECB/Diode, B/GB, DRRB)
- logic low
- logic high
Digital Inputs (DRRB Only)
4
VIL
-5
VIH
-2
-3
V
0
V
Logic Compatibility
Negative ECL
- logic low
- logic high
4
VIL
-1.810
VIH
-1.165
-1.625
V
-0.880
V
5
2101D–BDC–06/04
Share Link: 