UPD75P3216 데이터 시트보기 (PDF) - NEC => Renesas Technology

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UPD75P3216

4-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

µPD75P3216

3.2 Non-port Pins

Pin Name

I/O

Shared by

Function

Status

I/O Circuit

After Reset TypeNote 1

TI0

Input P13

External event pulse input to timer/event counter

Input

<B>-C

PTO0

Output P20

Timer/event counter output

Input

E-B

PTO1

P21

Timer counter output

PTO2

P22/PCL

PCL

P22/PTO2

Clock output

BUZ

P23

Any frequency output (for buzzer or system clock trimming)

SCK

I/O P01

Serial clock I/O

Input

<F>-A

SO/SB0

P02

Serial data output

Serial data bus I/O

<F>-B

SI/SB1

P03

Serial data input

Serial data bus I/O

<M>-C

INT4

Input P00

Edge detection vectored interrupt input

(detecting both rising and falling edges)

Input

<B>

INT0

KR0 to KR3

Input P10

Input P60/D0-P63/D3

Edge detection vectored interrupt input

(detected edge is selectable). INT0/P10

can select noise elimination circuit

Falling edge detection testable input

Noise elimination

circuit/asynch

is selectable

Input

<B>-C

Input

<F>-A

X1

Input

—

Ceramic/crystal oscillation circuit connection for system

—

—

clock. If using an external clock, input to X1 and input

X2

—

inverted phase to X2.

RESET

Input

—

System reset input

—

<B>

MD0 to MD3 Input P30 to P33

Mode selection for program memory (PROM) write/verify

Input

<F>-A

D0 to D3

I/O P60/KR0-P63/KR3 Data bus pin for program memory (PROM) write/verify.

Input

<F>-A

D4 to D7

P50 to P53

M-E

VPP

—

—

Programmable power supply voltage for program memory

—

—

(PROM) write/verify.

For normal operation, connect directly to VDD.

Apply +12.5 V for PROM write/verify.

VDD

—

—

Positive power supply

—

—

VSS

—

—

Ground

—

—

S12 to S15 Output

—

Segment signal output

Note 2

G-A

S16 to S19 Output P93 to P90

Segment signal output

Input

H

S20 to S23

P83 to P80

COM0 to COM3 Output

—

Common signal output

Note 2

G-B

VLC0 to VLC2

—

—

Power source for LCD drive

—

—

BIAS

Output

—

Output for external split resistor cut

Note 3

—

LCDCLNote 4 Output P30/MD0

SYNCNote 4

P31/MD1

Clock output for driving external expansion driver

Input

E-B

Clock output for synchronization of external expansion driver

Notes 1. Circuit types enclosed in brackets indicate Schmitt trigger circuits.

2. The VLCX (X = 0, 1, 2) shown below are selected as the input source for the display outputs.

S12 to S15: VLC1, COM1 to COM2: VLC2, COM3: VLC0

3. When the split resistor is incorporated : Low level

When the split resistor is not incorporated : High impedance

4. These pins are provided for future system expansion. Currently, only P30 and P31 are used.

7

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