USB100N24 데이터 시트보기 (PDF) - Fairchild Semiconductor
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USB100N24 Datasheet PDF : 8 Pages
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Absolute Maximum Ratings
Ambient Storage Temperatures
-65°C to + 150°C
All Input or Output Voltages with
respect to ground
VCC + 1 to – 0.3V
Lead Temperature
(Soldering, 10 seconds)
+300%
ESD Rating
2000V
Operating Conditions
Ambient Operating Temperature
Power Supply (VCC) Range
0°C to +70°C
4.4V to 5.5V
DC and AC Electrical Characteristics 4.4V ≤ VCC ≤ 5.5V
Symbol
Parameter
Conditions
Min
Max
Units
ICCA
ICCS
VIL
VIH
VOL
VOH
IIL
IOL
FSK
TSKH
TSKL
TCS
TCSS
TDH
TDIS
TCSH
TDIH
TPD1
TPD0
TSY
TDF
TWP
Operating Current
Standby Current
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
Input Leakage Current
Output Leakage Current
SK Clock Frequency
SK High Time
SK Low Time
Minimum CS Low Time
CS Setup Time
DO Hold Time
DI Setup Time
CS Hold Time
DI Hold Time
Output Delay to “1”
Output Delay to “0”
CS to Status Valid
CS to DO in TRI-STATE
Write Cycle Time
USB interface in active mode
USB interface in suspend
2
2.4
Note 3
0
250
250
Note 4
250
50
70
100
0
20
40
mA
500
µA
0.8
V
V
0.4
V
V
2.5
µA
2.5
µA
1
MHz
ns
ns
ns
ns
ns
ns
ns
ns
500
ns
500
ns
500
ns
100
ns
10
ms
AC Test Conditions
Timing Measurements Reference Level
Output Load
1 TTL Gate Input
1V and 2V
Input Pulse Levels
0.4V and 2.4V Output
0.8V and 2.0V
Note 1: Stress ratings above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and operation of the
device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Note 2: The shortest allowable S clock period = 1/fSK (as shown under the fSK parameter). Maximum SK clock speed (minimum SK period) is determined by the interaction of
several AC parameters stated in the datasheet. Within this SK period, both tSKH and tSKL limits must be observed. Therefore, it is not allowable to set 1/fSK = tSKH(minimum) +
tSKL(minimum) for shorter SK cycle time operation.
Note 3: CS (Chip Select) must be brought low (to VIL) for an interval of tCS in order to reset all internal device registers (device reset) prior to beginning another opcode cycle.
(This is shown in the opcode diagrams in the following pages.)
USB100 rev.D
3
www.fairchildsemi.com
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