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VRS1000 Datasheet PDF : 47 Pages
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VRS1000
VERSA
Datasheet Rev 1.6
Expanded RAM Access Using the MOVX @DPTR
Instruction (0000-02FF, Bank4-Bank15)
The 768 bytes of the expanded RAM data memory
occupy addresses 0000h to 02FFh. It can be accessed
using external direct addressing (i.e. using the MOVX
instruction) or by using bank mapping direct
addressing. Note that in the case of indirect addressing
using the MOVX @DPTR instruction, if the address is
larger than 02FFh, the VRS1000 will generate the
external memory control signal automatically.
Internal RAM Control Register
The 768 bytes of expanded RAM of the VRS1000 can
also be accessed using the MOVX @Rn instruction
(where n = 0,1). This instruction is only able to access
data in a range of 256 bytes. The internal RAM Control
Register RCON allows users to select which part of the
expanded RAM will be targeted by the instruction, by
configuring the value of the RAMS0 and RAMS1 bits.
The default setting of the RAMS1 and RAMS0 bits is
00 (page 0). Each page has 256 bytes.
TABLE 12: INTERNAL RAM CONTROL REGISTER (RCON) - SFR 85H
7
6
5
4
3
2
1
Unused
RAMS1
0
RAMS0
Bit Mnemonic Description
7 Unused
-
6 Unused
-
5 Unused
-
4 Unused
-
3 Unused
-
2 Unused
-
1 RAMS1
These two bits are used with Rn of instruction
0 RAMS0
MOVX @Rn, n=1,0 for mapping (see section
on extended 768 bytes)
RAMS1, RAMS0 Mapped area
00
000h-0FFh
01
100h-1FFh
10
200h-2FFh
11
XY00h-XYFF*
*Externally generated
Example:
Suppose that RAMS1, RAMS0 are set to 0 and 1
respectively and Rn has a value of 45h.
Performing MOVX @Rn, A, (where n is 0 or 1) allows the
user to transfer the value of A to the expanded RAM at
address 145h (page 1).
It is important to note that when both RAMS1, RAMS0
are set to 1, the value of P2 defines the upper byte of
the external address accessed. Rn defines the lower
byte of the address. In this case, the VRS1000 will
generate the external memory control signals
automatically. This allows users to access externally
mapped devices in the “P2value”00h to “P2value”FFh
range.
Data Bank Control Register
The DBANK register allows the user to enable the
Data Bank Select function and map the entire content
of the RAM memory in the range of 40h to 7Fh for
applications that would require direct addressing of the
expanded RAM content.
The Data Bank Select function is activated by setting
the Data Bank Select enable bit (BSE) to 1. Setting this
bit to zero disables this function. The four least
significant bits of this register controls the mapping of
the entire 1K byte on-chip RAM space into the 040h-
07Fh range.
TABLE 13: DATA BANK CONTROL REGISTER (DBANK) – SFR 86H
7
BSE
6
5
4
Unused
3
2
BS3 BS2
1
0
BS1 BS0
Bit Mnemonic Description
7
BSE
Data Bank Select Enable Bit
BSE=1, Data Bank Select enabled
BSE=0, Data Bank Select disabled
6
Unused
-
5
Unused
-
4
Unused
-
3
BS3
Allows the mapping of the 1K RAM into the
2
BS2
040h - 07Fh RAM space
1
BS1
0
BS0
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