MCZ33291EG 데이터 시트보기 (PDF) - Freescale Semiconductor
부품명
상세내역
제조사
MCZ33291EG Datasheet PDF : 27 Pages
| |||
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions 4.5 V ≤ VDD ≤ 5.5 V, 9.0 V ≤ VPWR ≤ 16 V, -40°C ≤ TA ≤ 125°C, unless otherwise noted.
Typical values noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING
Output Rise Time (VPWR = 13 V, RL = 26 Ω) (28)
Output Fall Time (VPWR = 13 V, RL = 26 Ω) (28)
Output Turn-ON Delay Time (VPWR = 13 V, RL = 26 Ω) (29)
Output Turn-OFF Delay Time (VPWR = 13 V, RL = 26 Ω) (30)
Output Short Fault Disable Report Delay (31)
SFPD = 0.2 x VDD
Output OFF Fault Report Delay (32)
SFPD = 0.2 x VDD
tR
0.4
5.0
20
μs
tF
0.4
5.0
20
μs
tDLY (ON)
1.0
15
50
μs
tDLY (OFF)
1.0
15
50
μs
tDLY (SF)
70
μs
150
250
tDLY (OFF)
70
μs
150
250
DIGITAL INTERFACE TIMING
Required Low State Duration for RST (VIL < 0.2 VDD) (33)
Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)
Falling Edge of SCLK to Rising Edge of CS (Required for Setup Time)
SI to Falling Edge of SCLK (Required for Setup Time)
Falling Edge of SCLK to SI (Required for Hold Time)
SO Rise Time (CL = 200 pF)
SO Fall Time (CL = 200 pF)
SI, CS, SCLK, Incoming Signal Rise Time (34)
SI, CS, SCLK, Incoming Signal Fall Time (34)
Time from Falling Edge of CS to SO Low Impedance (35)
Time from Rising Edge of CS to SO High Impedance (36)
Time from Rising Edge of SCLK to SO Data Valid (37)
0.2 VDD ≤ SO ≥ 0.8 VDD, CL = 200 pF
tW(RST)
–
tLEAD
–
tLAG
–
tSI (SU)
–
tSI (HOLD)
–
tR (SO)
–
tF (SO)
–
tR (SI)
–
tF (SI)
–
tSO(EN)
–
tSO(DIS)
–
tVALID
–
50
167
ns
50
167
ns
50
167
ns
25
83
ns
25
83
ns
25
50
ns
25
50
ns
–
50
ns
–
50
ns
–
110
ns
–
110
ns
ns
65
105
Notes
28. Output Rise and Fall time respectively measured across a 26 Ω resistive load at 10% to 90% and 90% to 10% voltage points.
29. Output Turn-ON Delay time measured from 50% rising edge of CS to 90% of Output OFF voltage (VPWR) with RL = 26 Ω resistive load.
30. Output Turn-OFF Delay time measured from 50% rising edge of CS to 10% of Output OFF voltage (VPWR) with RL = 26 Ω resistive load.
31. Propagation time of Short Fault Disable Report measured from 50% rising edge of CS to 10% Output OFF voltage (VPWR), VPWR =
6.0 V and SFPD = 0.2 x VDD.
32. Output OFF Fault Report Delay measured from 50% rising edge of CS to 10% rising edge of Output OFF voltage (VPWR).
33. RST Low duration measured with outputs enabled and going to OFF or disabled condition.
34. Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
35. Time required for output status data to be available for use at the SO pin.
36. Time required for output status data to be terminated at the SO pin.
37. Time required to obtain valid data out from SO following the rise of SCLK. See Figure 7, page 10.
33291
8
Analog Integrated Circuit Device Data
Freescale Semiconductor
Share Link: 