M24164-MN 데이터 시트보기 (PDF) - STMicroelectronics

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M24164-MN

16 Kbit Serial I²C Bus EEPROM with 1 Inverting and 2 Non-Inverting Chip Enable Lines

STMicroelectronics 

M24164

that is, the most significant memory address bits

are the same. If more bytes are sent than will fit up

to the end of the row, a condition known as ‘roll-

over’ occurs. This should be avoided, as data

starts to become overwritten in an implementation

dependent way.

The bus master sends from 1 to 16 bytes of data,

each of which is acknowledged by the device if

Write Control (WC) is Low. If Write Control (WC) is

High, the contents of the addressed memory loca-

tion are not modified, and each data byte is fol-

lowed by a NoAck. After each byte is transferred,

the internal byte address counter (the 4 least sig-

nificant address bits only) is incremented. The

transfer is terminated by the bus master generat-

ing a Stop condition.

Figure 8. Write Mode Sequences with WC=0 (data write enabled)

WC

BYTE WRITE

ACK

ACK

ACK

DEV SEL

BYTE ADDR

DATA IN

R/W

WC

PAGE WRITE

WC (cont'd)

PAGE WRITE

(cont'd)

ACK

ACK

ACK

ACK

DEV SEL

BYTE ADDR DATA IN 1

DATA IN 2

DATA IN 3

R/W

ACK

ACK

DATA IN N

AI02804

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