P4C1024-17J3C 데이터 시트보기 (PDF) - Performance Semiconductor
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P4C1024-17J3C Datasheet PDF : 8 Pages
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P4C1024
READ CYCLE NO. 1 (OE CONTROLLED)(1)
ADDRESS
OE
CE
CE2
DATA OUT
tAA
t OE
t
OLZ
tAC
t LZ
tRC(5)
tOH
t OHZ
t HZ
NOTES:
1. WE is HIGH for READ cycle.
2.
CE
1
and
OE
is
LOW
and
CE2
is
HIGH
for
read
cycle.
3. ADDRESS must be valid prior to, or coincident with later of
CE1 transition LOW or CE2 transition HIGH.
4. Transition is measured ± 200 mV from steady state voltage
prior to change, with loading as specified in Figure1. This
parameter is sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to
the first transitioning address.
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
ADDRESS
DATA OUT
t AA
t OH
PREVIOUS DATA VALID
tRC (5)
DATA VALID
READ CYCLE NO. 3 (CE CONTROLLED)
tRC
CE1
CE2
DATA OUT
ICC
VCC SUPPLY ISB
CURRENT
tAC
tLZ
tPU
tHZ
DATA VALID
tPD
HIGH IMPEDANCE
144
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