LH28F008SCT-V12 데이터 시트보기 (PDF) - Sharp Electronics

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LH28F008SCT-V12

8 M-bit (1 MB x 8) Smart 5 Flash Memories

Sharp Electronics 

1 INTRODUCTION

This datasheet contains LH28F008SC-V/SCH-V

specifications. Section 1 provides a flash memory

overview. Sections 2, 3, 4, and 5 describe the

memory organization and functionality. Section 6

covers electrical specifications. LH28F008SC-V/

SCH-V flash memories documentation also

includes ordering information which is referenced in

Section 7.

1.1 New Features

LH28F008SC-V/SCH-V Smart 5 flash memories

maintain backwards-compatibility with the

LH28F008SA. Key enhancements over the

LH28F008SA include :

• Smart 5 Technology

• Enhanced Suspend Capabilities

• In-System Block Locking

Both devices share a compatible pinout, status

register, and software command set. These

similarities enable a clean upgrade from the

LH28F008SA to LH28F008SC-V/SCH-V. When

upgrading, it is important to note the following

differences :

• Because of new feature support, the two

devices have different device codes. This

allows for software optimization.

• VPPLK has been lowered from 6.5 V to 1.5 V to

support 5 V block erase, byte write, and lock-bit

configuration operations. Designs that switch

VPP off during read operations should make

sure that the VPP voltage transitions to GND.

• To take advantage of Smart 5 technology, allow

VPP connection to 5 V.

1.2 Product Overview

The LH28F008SC-V/SCH-V are high-performance

8 M-bit Smart 5 flash memories organized as 1 M-

byte of 8 bits. The 1 M-byte of data is arranged in

sixteen 64 k-byte blocks which are individually

LH28F008SC-V/SCH-V

erasable, lockable, and unlockable in-system. The

memory map is shown in Fig.1.

Smart 5 technology provides a choice of VCC and

VPP combinations, as shown in Table 1, to meet

system performance and power expectations. VPP

at 5 V eliminates the need for a separate 12 V

converter, while VPP = 12 V maximizes block erase

and byte write performance. In addition to flexible

erase and program voltages, the dedicated VPP pin

gives complete data protection when VPP ≤ VPPLK.

Table 1 VCC and VPP Voltage Combinations

Offered by Smart 5 Technology

VCC VOLTAGE

5V

VPP VOLTAGE

5 V, 12 V

Internal VCC and VPP detection circuitry auto-

matically configures the device for optimized read

and write operations.

A Command User Interface (CUI) serves as the

interface between the system processor and

internal operation of the device. A valid command

sequence written to the CUI initiates device

automation. An internal Write State Machine (WSM)

automatically executes the algorithms and timings

necessary for block erase, byte write, and lock-bit

configuration operations.

A block erase operation erases one of the device’s

64 k-byte blocks typically within 1 second (5 V VCC,

12 V VPP) independent of other blocks. Each block

can be independently erased 100 000 times (1.6

million block erases per device). Block erase

suspend mode allows system software to suspend

block erase to read data from, or write data to any

other block.

Writing memory data is performed in byte

increments typically within 6 µs (5 V VCC, 12 V

VPP). Byte write suspend mode enables the system

-5-

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