LH28F008SCT-V12 데이터 시트보기 (PDF) - Sharp Electronics

부품명

상세내역

제조사

LH28F008SCT-V12

8 M-bit (1 MB x 8) Smart 5 Flash Memories

Sharp Electronics 

3.5 Read Identifier Codes Operation

The read identifier codes operation outputs the

manufacture code, device code, block lock

configuration codes for each block, and the master

lock configuration code (see Fig. 2). Using the

manufacture and device codes, the system CPU

can automatically match the device with its proper

algorithms. The block lock and master lock

configuration codes identify locked and unlocked

blocks and master lock-bit setting.

FFFFF

F0004

F0003

F0002

F0001

F0000

Reserved for

Future Implementation

Block 15 Lock Configuration Code

Reserved for

Future Implementation

Block 15

(Blocks 2 through 14)

1FFFF

10004

10003

10002

10001

10000

0FFFF

00004

00003

00002

00001

00000

Reserved for

Future Implementation

Block 1 Lock Configuration Code

Reserved for

Future Implementation

Block 1

Reserved for

Future Implementation

Master Lock Configuration Code

Block 0 Lock Configuration Code

Device Code

Manufacture Code Block 0

Fig. 2 Device Identifier Code Memory Map

LH28F008SC-V/SCH-V

3.6 Write

Writing commands to the CUI enable reading of

device data and identifier codes. They also control

inspection and clearing of the status register. When

VPP = VPPH1/2, the CUI additionally controls block

erasure, byte write, and lock-bit configuration.

The Block Erase command requires appropriate

command data and an address within the block to

be erased. The Byte Write command requires the

command and address of the location to be written.

Set Master and Block Lock-Bit commands require

the command and address within the device

(Master Lock) or block within the device (Block

Lock) to be locked. The Clear Block Lock-Bits

command requires the command and address

within the device.

The CUI does not occupy an addressable memory

location. It is written when WE# and CE# are

active. The address and data needed to execute a

command are latched on the rising edge of WE# or

CE# (whichever goes high first). Standard

microprocessor write timings are used. Fig. 13 and

Fig. 14 illustrate WE# and CE#-controlled write

operations.

4 COMMAND DEFINITIONS

When the VPP voltage ≤ VPPLK, read operations

from the status register, identifier codes, or blocks

are enabled. Placing VPPH1/2 on VPP enables

successful block erase, byte write and lock-bit

configuration operations.

Device operations are selected by writing specific

commands into the CUI. Table 3 defines these

commands.

-9-

Share Link: